A FPGA high-speed transceiver and its dynamic control method

Abstract

The invention discloses an FPGA high-speed transceiver and a dynamic control method thereof, the FPGA high-speed transceiver comprises a high-speed transceiver, a clock chip, an FPGA control unit andan interface unit, the high-speed transceiver is used for providing a high-speed serial data interface; the clock chip is used for dividing an input clock frequency into four paths of output clocks; the FPGA control unit is used for controlling initialization and output frequency change of the clock chip; the interface unit is used for transmitting a control instruction of the FPGA control unit tothe clock chip. According to the invention, the reference clock of the high-speed transceiver is dynamically adjustable within a certain range, so that the difference between the reference clock andthe clock frequency of the input data is within the CDR frequency deviation tolerance, and the high-speed port is ensured to receive the data correctly. The invention further discloses a dynamic control method of the FPGA high-speed transceiver, the high-speed port can correctly recover the clock and the data under the condition of non-cooperative communication, and a control circuit of the FPGA high-speed transceiver is simple, easy to implement, stable and reliable.

Description

technical field [0001] The invention relates to the technical field of electronic engineering, in particular to an FPGA high-speed transceiver and a dynamic control method thereof. Background technique [0002] FPGA (Field-Programmable Gate Array) is a field programmable gate array. As a programmable device, it not only solves the shortcomings of application-specific integrated circuits, but also overcomes the shortcomings of the limited number of logic gates in programmable devices. FPGA integrates a large number of original logic resources such as flip-flops, look-up table LUTs, and wiring, and provides configurable I / O ports and hard IP (GTx, BlockRAM, PLL, general-purpose interfaces, etc.), relying on engineers to use hardware description language (HDL , HardwareDescriptionLanguage) to encode, and each logic works in parallel to achieve the specified function. [0003] High-speed transceiver GTx (Gigabit Transceiver) is a high-speed serial interface developed by Xilinx ...

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Problems solved by technology

[0005] However, the above method has the following disadvantages: the premise of the above method is that the oscillation frequency of the reference clock is very close to the frequency of the input data, and the frequency of the local clock obtained after being multiplied by the phase-locked loop is usually only a few hundred ppm (hundreds of ppm) different from the frequency of the input data. ten thousandth)

But in the case of non-cooperative communication, the input data rate and its approximate range are usually unknown

When the input data rate is unknown, the frequency difference between the local clock input and the data rate is likely to far exceed the frequency deviation tolerance of the CDR unit, resulting in the inability to correctly recover the data at the sending end

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