A system and method for encrypting and decrypting network data packets

Abstract

The present invention proposes a system for network data packet encryption and decryption processing, including: CPU writes a command word to the command word FIFO to indicate that the network data packet to be encrypted and decrypted is ready, and triggers the forward DMA module; and write the source address, data length and destination address information of the network packet to be encrypted and decrypted into the forward data manager; the forward DMA module writes the forward data in the forward data manager The source address and data length information of the network data packet to be encrypted and decrypted are written in the channel data command word FIFO; the command word triggers the forward DMA module again, and the source address, data length and data length of the network data packet to be encrypted and decrypted are The destination address is transferred to the forward buffer, and the network data packet to be encrypted and decrypted is transferred to the forward buffer according to the source address and data length for the encryption and decryption module to perform encryption and decryption processing. The invention can reduce the copy of encryption and decryption processing, lighten the burden of CPU, and improve the efficiency of encryption and decryption.

Description

technical field [0001] The invention relates to the technical field of data communication, in particular to a system and method for encrypting and decrypting network data packets. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, Field Programmable Gate Array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. [0003] In the information age where information security is increasingly valued, the processing of network data packets also needs to have encryption and decryption functions. To meet this requirement, the FPGA chip is equipped with an encryption and decryption module for encryption and decryption of network data packets; currently, When ...

AI Technical Summary

Problems solved by technology

[0003] In the information age where information security is increasingly valued, the processing of network data packets also needs to have encryption and decryption functions. To meet this requirement, the FPGA chip is equipped with an encryption and decryption module for encryption and decryption of network data packets; currently, When the data packet received by the network card needs to be sent to the encryption and decryption module of the FPGA for encryption and decryption processing, the traditional processing method is to configure the forward and reverse data packet buffer space for the encryption and decryption module, and then the host will receive the network data from the network card. The data packet is copied to the buffer space of the forward data packet space to be read. After the encryption and decryption is completed, the network data packet is stored in the reverse data packet buffer space, and then the network data packet is copied to the buffer set by the network card through the host. Send after the zone, this method has more memory copies of network data packets, which increases the burden on the CPU

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