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In-memory data pooling device and method for machine learning

A data pooling and pooling technology, applied in complex mathematical operations, biological neural network models, neural architectures, etc., can solve problems such as performance reduction and power consumption

Pending Publication Date: 2020-05-01
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this data movement can consume a significant amount of power and degrade performance

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  • In-memory data pooling device and method for machine learning
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  • In-memory data pooling device and method for machine learning

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Embodiment Construction

[0088] The following description will generally refer to specific structural embodiments and methods. It should be understood that there is no intention to limit the technology to the embodiments and methods disclosed in detail, but that other features, elements, methods and embodiments can be used to implement the technology. The preferred embodiments are described to illustrate the technology, not to limit its scope, which is defined by the claims. Those skilled in the art will recognize various equivalent changes in the description that follows.

[0089] figure 1 An exemplary device 100 is shown comprising: a first block of memory cells 110 for storing an input array; and a second block of memory cells 130 for storing an output array. The apparatus includes a pooling circuit (1140, Figure 11 ) that performs in-place pooling according to a function on an input array to produce an array of output values. The device includes write circuitry operatively coupled to the seco...

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Abstract

A data pooling method comprises a first block of memory cells to store an input array, and a second block of memory cells. Pooling circuitry is operatively coupled to the first block of memory cells to execute in-place pooling according to a function over the input array to generate an array of output values. Writing circuitry is operatively coupled to the second block to store the array of outputvalues in the second block of memory cells. Analog sensing circuitry is coupled to the first block of memory cells to generate analog values for the input array, wherein the pooling circuitry receives the analog values as inputs to the function. The writing circuitry operatively coupled to the second block is configured to store an analog level in each cell of the second block for the array of output values.

Description

technical field [0001] The present invention relates to a circuit that can be used to perform in-memory compression for machine learning. Background technique [0002] Convolutional Neural Network (CNN) is used in machine learning with applications in many fields, such as speech recognition, computer vision and word processing. CNN operations may be implemented using a system including Graphics Processing Units (GPU) and a Dynamic Random Access Memory (DRAM) coupled to the GPU. In such a system, data is frequently moved between multiple GPUs and DRAMs for convolution and pooling operations via components on the printed circuit board, such as conductive traces and pads. However, such data movement can consume significant amounts of power and degrade performance. [0003] It would be desirable to provide a device for pooling operations that improves performance and reduces power consumption. Contents of the invention [0004] The present invention provides a device compri...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063
CPCG06N3/063G06N3/045Y02D10/00G06F17/16G06F17/18G06N3/065
Inventor 龙翔澜
Owner MACRONIX INT CO LTD