Hardware SAT solver for multi-thread parallel execution

A multi-threaded, solver technology, applied in the computer field, can solve the problems of lack of fast memory and high overhead, and achieve the effect of high solving success rate, avoiding time overhead, and reducing resource overhead.

Active Publication Date: 2020-05-15
NAT UNIV OF DEFENSE TECH
View PDF2 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] For hardware solvers based on full algorithms, the lack of sufficient fast memory is the main reason why previous work did not try multi-threaded BCP in ha

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Hardware SAT solver for multi-thread parallel execution
  • Hardware SAT solver for multi-thread parallel execution
  • Hardware SAT solver for multi-thread parallel execution

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0039] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0040] The hardware SAT solver of a kind of multi-thread parallel execution of the present invention adopts FPGA technology to realize, and all data of the solver are all stored in the on-chip memory of FPGA, have avoided because the time overhead that reads off-chip data brings, can reach Maximum performance. At the same time, the multi-thread strategy is used to greatly reduce the resource overhead of the on-chip memory, and the total turnover per second is doubled, and the solution success rate is high.

[0041] In an optional embodiment, the present invention provides a structure of a hardware SAT solver executed in parallel by multiple threads, such as figure 1 As shown, it includes a f...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a hardware SAT solver for multi-thread parallel execution. The hardware SAT solver comprises a first register module, a first evaluation module group, a buffer module group, a counter module, a variable element overturning module, a probability mapping table, an FIFO tree group, a second register module group, a second evaluation module and a third register module. All the data is stored in an on-chip memory of an FPGA; time expenditure caused by reading off-chip data is avoided. Meanwhile, a multi-thread strategy is utilized; different threads interact with the same address mapping table and clause mapping table. Compared with the prior art, the invention has the advantages that the resource overhead of the on-chip memory is greatly reduced, the total flipping amount per second is multiplied due to the use of a multi-thread strategy, the solution of the problem is more likely to be found in the specified time, and the relatively large-scale SAT problem can be solved more efficiently and conveniently.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to a SAT solver, in particular to a hardware SAT solver for multi-thread parallel execution. Background technique [0002] In the SAT problem (satisifiability problem, Boolean satisfiability problem), given a set of finite variable set X={x 1 ,x 2 ,...,x n}, x n Can be assigned true (1) or false (0), the literal l i is the variable x i or its negation and have Clause C is formed by text disjunction (meaning "or"), and the conjunction normal form CNF (conjectured normal formula) formula Formed by the conjunction of several clauses, such as That is, a CNF formula consisting of 5 variables and 4 clauses. If any word in a clause is assigned a value of true, then the clause is true or satisfied; if all the words in a clause are assigned a value of false at the same time, it is said that the specified assignment makes the clause false, or the specified assignm...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F17/10
CPCG06F17/10
Inventor 黎铁军马柯帆张建民常俊胜孙岩翦杰王强熊泽宇肖灿文徐佳庆
Owner NAT UNIV OF DEFENSE TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products