Dynamic storage buffer area reading control method based on power edge gateway
A dynamic storage, edge gateway technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve the problem of data storage buffer channel blockage, etc., to achieve the effect of dynamic reading and avoiding overflow
Active Publication Date: 2020-09-29
JIANGSU FRONTIER ELECTRIC TECH
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Problems solved by technology
[0004] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is to avoid the blockage of the channel of the data storage buffer, and to improve the efficiency of the pipeline structure by adopting the method of counting
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Embodiment 1
[0022] see figure 1 , for the purpose of illustration, M is the current count value of the counting module, X is the data amount of a read request of the DDR read request generation module, and Y is the amount of read data received from the read data FIFO by the DDR data user. refer to image 3 , the DDR read request generation module initiates three read requests, and the DDR data user initiates two read data FIFO operations. Assuming that the storage capacity of the read data FIFO is 64, that is, 64 pieces of data matching the FIFO bit width can be stored. Therefore, the initial count value of the current count value M of the counting module is 64. After k clocks have elapsed, see figure 2 , the DDR read request generation module detects that the read request FIFO is not full. And the current count value 64 is greater than the number of data to be read this time 32, therefore, the write enable signal req_fifo_en of the read request FIFO is valid, and at the same time, t...
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The invention discloses a dynamic storage buffer area based on a power edge gateway and a reading control method. The invention relates to the field of data storage, super computing, information systems and the like, and particularly relates to a DDR data usage module and a DDR data transmission module, the DDR data transmission module comprises a read request FIFO, a DDR read controller, a DDR memory and a read data FIFO; the DDR data use module comprises a DDR read request generation module, a DDR data use terminal and a counting module; according to the dynamic storage buffer area reading control method provided by the invention, the counting module and the two cache FIFOs are utilized, and the counting value of the counting module is compared with the reading request data volume, so that the dynamic reading of the cache data of the DDR memory is effectively realized, and the overflow of the data and the storage congestion of the reading data FIFOs are avoided.
Description
technical field [0001] The invention relates to the field of electrical engineering science, in particular to the fields of data storage, supercomputing, and information systems, and in particular to a dynamic storage buffer reading control method based on an electric edge gateway. Background technique [0002] With the rapid development of information technology, how to achieve efficient storage of large-capacity data has gradually become an urgent problem to be solved. DDR memory uses an advanced synchronous circuit, so that the main steps of the specified address, data transmission and output are executed independently and fully synchronized with the CPU. At the same time, DLL (Delay Locked Loop, delay locked loop provides a data filter signal) technology is used. When the data is valid, the memory controller can use this data filter signal to accurately locate the data. In essence, it can be doubled without increasing the clock frequency. Increases the speed of SDRAM, w...
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Login to View More IPC IPC(8): G06F12/0877G06F12/0893G06F5/06
CPCG06F12/0877G06F12/0893G06F5/06
Inventor 李澄李春鹏徐妍宋庆武单华李军
Owner JIANGSU FRONTIER ELECTRIC TECH