Cache design method and cache design device for parallel double channels

Abstract

The invention discloses a cache design method and device for parallel double channels. In the first pipeline stage, the addresses of two new instructions newly enqueued in the double channels are obtained, address conflict detection is conducted on the addresses of the new instructions and all the addresses of the old instructions before the double channels are enqueued in the double channels, anddifferent operations are executed according to the difference of conflict instructions; in the second pipeline stage, the tag area of the new instruction is compared with the tag area of the L1 cache, and hit or miss information of the new instruction is obtained; in the third pipelining stage, according to whether the new instruction is operated or not and whether the L1 cache is hit or not, corresponding operation is carried out, so that the technical problem that the out-of-order execution efficiency of the processor is relatively low due to the fact that parallel execution of the storageinstructions is limited because the read or write instructions share one storage channel in the existing single-channel cache design is solved.

Description

technical field [0001] The present application relates to the technical field of processors, in particular to a parallel dual-channel cache design method and device. Background technique [0002] With the development of architecture and technology, the computing power of processors has also developed rapidly. From 33MHz in 1990 to more than 3GHz in 2020, the frequency of CPU has increased hundreds of times. As the single-core frequency continues to increase, it will bring huge heat and power consumption. In order to continue to improve processor performance, multi-core technology has emerged as the times require, from single-core to hundreds of cores. The central idea of ​​multi-core is to divide a large task into multiple subtasks and distribute them to multiple cores for execution. Therefore, most of the current processor designs use a combination of high-frequency + multi-core solutions to achieve a balance between performance and power consumption. [0003] At present...

AI Technical Summary

Problems solved by technology

[0004] The present application provides a parallel dual-channel cache design method and device, which is used to solve the problem that in the existing single-channel cache design, the read or write instructions share one storage channel, which limits the parallel execution of storage instructions and causes the processor to execute out of order less efficient technical issues

Images