Variable format, variable sparsity matrix multiplication instruction

A sparse matrix and matrix technology, applied in the field of computer processor architecture, can solve problems such as lack of flexibility

Pending Publication Date: 2020-12-18
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Some traditional matrix multiplication methods are specialized, such as they lack the flexibility to support various data formats (signed and unsigned 8b / 16b integers, 16b floating point) with wide accumulators, and the flexibility to support dense and sparse matrices

Method used

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  • Variable format, variable sparsity matrix multiplication instruction
  • Variable format, variable sparsity matrix multiplication instruction
  • Variable format, variable sparsity matrix multiplication instruction

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Embodiment Construction

[0038] In the following description, numerous specific details are set forth. However, it is understood that some embodiments may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

[0039] References in the specification to "one embodiment," "an embodiment," "exemplary embodiment," etc. indicate that the described embodiments may include a feature, structure, or characteristic, but that each embodiment may not necessarily include the feature, structure, or characteristic. structure or feature. Moreover, these phrases are not necessarily referring to the same embodiment. Furthermore, when a feature, structure or characteristic is described with respect to an embodiment, it is considered to be within the knowledge range of those skilled in the art to affect such a feature, structure or characteristic with respect to other em...

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Abstract

Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M * K), (K * N), and (M * N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: routeeach row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M * N) processing array, and route each column of the specified B matrix, staggering subsequent columns,into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having the same row address as acolumn address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.

Description

[0001] Case Description [0002] This application is a divisional application of an invention patent application with the filing date on May 22, 2019, the application number 201910431218.5, and the title "Variable Format, Variable Sparse Matrix Multiplication Instruction". technical field [0003] The field of the invention relates generally to computer processor architecture and, in particular, to variable format, variable sparse matrix multiply instructions. Background technique [0004] Machine learning architectures such as deep neural networks have been applied in domains including computer vision, speech recognition, natural language processing, audio recognition, social network filtering, machine translation, bioinformatics, and drug design. Deep learning is a class of machine learning algorithms. Maximizing the flexibility and cost-efficiency of deep learning algorithms and computations can help meet the needs of deep learning processors, such as those performing d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F7/523G06F17/16
CPCG06F9/30036G06F9/30145G06F7/523G06F17/16G06N3/063G06F9/3001G06F9/3016G06N20/00
Inventor 马克·A·安德斯希曼殊·考尔萨努·马修
Owner INTEL CORP
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