A data addressing method, storage device, chip and data storage system

Abstract

A data addressing method, a storage device, a chip, and a data storage system. The data addressing method includes: configuring a mapping relationship between a first base address register and a memory space, and transferring data received by the first base address register to the The memory space to which the first base address register has a mapping relationship. The above-mentioned technical solution of the present invention has the following beneficial technical effects. In the embodiment of the present application, on the one hand, the software and hardware of the present invention are co-designed to achieve the internal addressing of a large-scale soc only by the host computer without the intervention of the internal cpu of the Pcie endpoint device soc. . On the other hand, the upper computer can configure the mapping address and storage space size of the second base address register to the first base address register through the second base address register to achieve the purpose of sliding window; and both first base address registers can Make the host computer access the register space inside the Pcie endpoint device chip, so that the host computer and the Pcie endpoint device can perform large-scale soc internal addressing.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a data addressing method, a storage device, a chip and a data storage system. Background technique [0002] Under the basic pcie protocol, the host computer addressing PCie endpoint devices only supports fixed base address register space addressing. Although the base address register can be set to GB-level space, due to the memory limitation of the host computer, the address range that can be reserved for the host computer is only It can be in the order of MB, so addressing the Pcie endpoint device through the host computer can generally only address the space in the order of MB. [0003] For the situation where the host computer needs to be used to address PCie endpoint devices in a large range, DMA (DirectMemoryAccess memory direct access) is generally used for addressing, which is suitable for using a small amount of base address register space for instruction interact...

AI Technical Summary

Problems solved by technology

Therefore, DMA addressing is only suitable for the transfer between the upper computer and the Pcie endpoint device of a large continuous code, and it will be extremely time-consuming when the short data is transferred.

In addition, if you need to start the whole chip through the pcie interface, if you use DMA addressing, the power-on scheme of the chip will be extremely complicated and difficult to implement

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