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Subsampling phase-locked loop

A phase-locked loop, slew rate technology, applied in the direction of electrical components, automatic power control, etc., can solve the problem of unstable phase-locked loop performance and other issues

Pending Publication Date: 2021-04-30
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] In a phase-locked loop, its bandwidth will be affected by multiple parameters, such as the current of the charge pump, the coefficient of the frequency divider, and the gain of the voltage-controlled oscillator, etc., and these parameters will be easily affected by process, voltage, and temperature deviations. Shift (process-voltage-temperature (PVT) variations), resulting in unstable performance of the phase-locked loop

Method used

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Examples

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Embodiment Construction

[0010] figure 1 It is a schematic diagram of a sub-sampling phase-locked loop (sub-sampling phase-locked loop) 100 according to an embodiment of the present invention. Such as figure 1 As shown, the sub-sampling phase-locked loop 100 includes a pulse signal generating circuit 110, a first charge pump 120, a phase detector 130, a buffer 140, an oscillator 150, a slew rate control circuit 160, a pulse width The control circuit 170, a coarse frequency selection circuit 180, a phase frequency detector 192, a second charge pump 194, a frequency divider 196, capacitors CP, CS and a resistor RS.

[0011] In the basic operation of the sub-sampling phase-locked loop 100, the pulse signal generating circuit 110 is used to receive a reference frequency signal CK_REF to generate a pulse signal Vp; the phase detector 130 uses the reference frequency signal CK_REF to sample a feedback signal CK_FB to Generate a first phase detection result Vsam; the first charge pump 120 generates a first...

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Abstract

The invention discloses a subsampling phase-locked loop. The subsampling phase-locked loop comprises a phase detector, a charge pump, an oscillator and a buffer, in operation of the subsampling phase-locked loop, the phase detector uses a reference frequency signal to sample a feedback signal to generate a first phase detection result, and the charge pump generates a control signal according to the first phase detection result and a pulse signal; the oscillator generates an output frequency signal according to the control signal; and the buffer is used for receiving the output frequency signal, generating the feedback signal and controlling the slew rate of the feedback signal according to a slew rate control signal.

Description

technical field [0001] The present invention relates to subsampling phase locked loops. Background technique [0002] In a phase-locked loop, its bandwidth will be affected by multiple parameters, such as the current of the charge pump, the coefficient of the frequency divider, and the gain of the voltage-controlled oscillator, etc., and these parameters will be easily affected by process, voltage, and temperature deviations. Due to the influence of process-voltage-temperature (PVT) variations, the performance of the phase-locked loop is unstable. Contents of the invention [0003] Therefore, one of the objectives of the present invention is to provide a sub-sampling phase-locked loop that can provide a stable bandwidth to solve the problems described in the prior art. [0004] In one embodiment of the present invention, a sub-sampling phase-locked loop is disclosed, which includes a first phase detector, a first charge pump, an oscillator and a first buffer. In the oper...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/18H03L7/085H03L7/107
CPCH03L7/18H03L7/085H03L7/1072
Inventor 杨育哲陈家源吕咏儒刘深渊
Owner REALTEK SEMICON CORP
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