Soft error reinforcement method applied to combinational logic circuit

A combined logic circuit and soft error technology, applied to logic circuits with logic functions, etc., can solve problems such as large area costs, and achieve the effects of high reliability assurance, flexible reinforcement solutions, and efficient reinforcement solutions

Active Publication Date: 2021-05-25
FUDAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the traditional method of three-mode redundancy reinforceme

Method used

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  • Soft error reinforcement method applied to combinational logic circuit
  • Soft error reinforcement method applied to combinational logic circuit
  • Soft error reinforcement method applied to combinational logic circuit

Examples

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Example Embodiment

[0067] Embodiment: A combined circuit reinforcement method, including four processes, such as figure 1 shown. They are the circuit reading process (110), the marking process of the logic gate to be strengthened (120), the grouping process (130) and the strengthening process (140) of the logic gate to be strengthened. figure 1 100 is the target reinforcement circuit, and the target circuit of this embodiment is figure 2 shown. figure 1 101 is the information of the logic gate to be reinforced selected in the target circuit, and the logic gate to be reinforced in this embodiment is figure 2 Logic gates marked with red circles in . figure 1 103 is the output circuit of the target circuit after being strengthened by the strengthening method of the present invention.

[0068] In this embodiment, the circuit reading process specifically includes the following steps:

[0069] (1) read in figure 2 As shown in the combined circuit, the whole circuit is regarded as a directed g...

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Abstract

The invention belongs to the technical field of semiconductors and integrated circuits, and particularly relates to a soft error reinforcement method applied to a combinational logic circuit. The method comprises four processes of reading, marking, grouping and reinforcing. In the reading process, the connection relation between the composition elements of the process extraction circuit and the elements; in the marking process, the to-be-reinforced logic gates are classified and marked, and the number and the positions of the to-be-reinforced logic gates can be randomly selected according to design requirements; in the grouping process, a specific grouping scheme is obtained through a method for solving all maximum connected sub-graphs of a directed graph formed by the logic gate to be reinforced; in the reinforcement process, the original circuit is subjected to grouped triple modular redundancy reinforcement, and the reinforced circuit is output. The invention has the advantages that on one hand, the combined circuit is reinforced based on triple modular redundancy, and high reliability guarantee can be provided; and on the other hand, a flexible and efficient reinforcement scheme can be provided, and compared with a traditional triple modular redundancy reinforcement scheme, more diversified circuit design requirements can be met.

Description

technical field [0001] The invention belongs to the technical field of semiconductors and integrated circuits, and in particular relates to a soft error reinforcement method applied to combinational logic circuits in integrated circuits. Background technique [0002] As semiconductor feature sizes continue to shrink, integrated circuits are increasingly susceptible to soft errors caused by radiation particle attacks. When a radiation particle attack occurs in a combinational logic circuit, an erroneous transient signal will be generated on the attacked circuit node. The error signal propagates along the logic path and is captured by the storage unit, and finally enters the key modules of the system, which may cause functional errors in the entire system. Such non-permanent errors are called soft errors. For electronic equipment with the risk of radiation attack and electronic systems with high reliability requirements, such as electronic equipment in spacecraft, aircraft a...

Claims

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Application Information

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IPC IPC(8): H03K19/20
CPCH03K19/20
Inventor 程旭谭驰誉韩军曾晓洋
Owner FUDAN UNIV
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