Unlock instant, AI-driven research and patent intelligence for your innovation.

A method and computing system based on gpgpu reconfigurable architecture

A computing system and computing unit technology, applied in the computing field, can solve the problems of convolution not being able to bypass matrix operations, loss of flexibility, narrow application scenarios, etc.

Active Publication Date: 2021-09-21
METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0064] 1. Reshape and Duplicate are performed on Tensor during the calculation of convolution to matrix, which will increase bandwidth consumption;
[0065] 2. The execution in the time domain brings repeated data loading, which is not as high as the energy efficiency ratio of the air domain execution of the systolic array
[0067] 1. Loss of flexibility. When the neural network model is continuously updated and iterated, it cannot flexibly support all GEMM acceleration algorithms, cannot support general-purpose operations other than matrix operations, and narrow application scenarios will lead to reduced market demand.
[0068] 2. There are still certain limitations here, that is, they only use the accumulation characteristics of the airspace, but completely abandon the time-domain accumulation characteristics of GPGPU, so that the convolution still cannot bypass the matrix operation

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A method and computing system based on gpgpu reconfigurable architecture
  • A method and computing system based on gpgpu reconfigurable architecture
  • A method and computing system based on gpgpu reconfigurable architecture

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0211] In meteorological simulation, the matrix multiplication operation representing state transition is the core of simulation calculation. Therefore, the user can set the arch_mode parameter to 0, that is, configure the registers in the computing system as a GPGPU architecture for fast matrix operations and data reading and writing.

example 2

[0213] In DNNs, fully connected (FC) operations are equivalent to matrix operations. Therefore, the user can set the arch_mode parameter to 0, that is, configure the registers in the computing system as a GPGPU architecture for fast matrix operations and data reading and writing.

example 3

[0215] In signal processing, convolutions (i.e. filtering, sliding windows, or so-called correlation or convolution operations) are widely used in image filtering. Users can set the arch_mode parameter to 1 to configure the registers in the computing system as a mixed systolic array architecture suitable for CNN to perform fast convolution operations.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method and a computing system based on a GPGPU reconfigurable architecture. The method includes selecting an architecture mode according to the participation degree of matrix multiplication or convolution operation in the calculation, wherein the architecture mode includes a general-purpose graphics processor mode and Hybrid systolic array mode; when the general-purpose graphics processor mode is selected, the registers in the computing system are configured to perform data access and operation in the general-purpose matrix multiplication mode of the general-purpose graphics processor; when the hybrid systolic array mode is selected, the computing system The registers are configured to perform data access and operations in a direct convolution manner with a hybrid systolic array. The computing system includes registers, and the architectural pattern of the registers is configured using the method described above. The method and computing system based on the GPGPU reconfigurable architecture disclosed by the present invention can be flexibly configured according to the needs of different scenarios, which can not only meet the general requirements, but also make up for the shortcomings of the lack of flexibility of special accelerators.

Description

technical field [0001] The present invention relates to the computing field, and more specifically to a method and a computing system based on a GPGPU reconfigurable architecture. Background technique [0002] Deep neural network (DNN) is the basis of current artificial intelligence (AI) applications, such as: speech recognition, image recognition, video processing, automatic driving, cancer detection, game confrontation, etc., and in some fields, DNN has surpassed human accuracy sex. [0003] figure 1 shows a relatively simple neural network calculation process: the neurons in the input layer pass the received information to the middle layer of the neural network (also known as the hidden layer), and the "weight sum" of the hidden layer is finally transmitted to the output layer, and finally presented to the user. The input or output of a neuron is usually called "activation", and the synapse is called "weight". In the present invention, including the specification and ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/16G06F17/15G06N3/04G06N3/063G06N3/08G06T1/20
CPCG06F17/16G06F17/15G06N3/063G06N3/08G06T1/20G06N3/045
Inventor 李颖
Owner METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD