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Code generation/execution method, device, device, storage medium

A code generation and code execution technology, applied in the field of processors, can solve problems such as reducing processor execution efficiency, affecting execution effects, long execution time, etc., to achieve the effect of ensuring execution efficiency and execution effect

Active Publication Date: 2021-09-28
北京壁仞科技开发有限公司 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this implementation will reduce the execution efficiency of the processor and affect the execution effect, for example, it will cause longer compilation time, larger executable code data volume and longer execution time

Method used

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  • Code generation/execution method, device, device, storage medium
  • Code generation/execution method, device, device, storage medium
  • Code generation/execution method, device, device, storage medium

Examples

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Embodiment Construction

[0054] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0055] In addition, as shown in the present disclosure and claims, the words "a", "an", "an" and / or "the" are not specific to the singular and may include the plural unless the context clearly suggests an exception. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, "comprising" or "comprises" and similar words mean that ...

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PUM

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Abstract

The present disclosure provides a code generation / execution method, device, device, and storage medium for multiple execution modes of a processor. In the code execution method, executable codes for multiple execution modes are generated according to the following steps: obtaining user codes, wherein the user codes include multiple code parts; Determining at least one differentially executed code portion that requires differential execution among the plurality of code portions; according to the calling relationship between the multiple code portions, generating multiple differentially executable codes respectively corresponding to multiple execution modes for the differentially executed code portion ; and according to the calling relationship between the multiple code parts, generate a shared executable code corresponding to multiple execution modes for at least one code part in the multiple code parts except the difference execution code part, wherein, The code execution method includes: for multiple execution modes, executing executable codes at least composed of multiple copies of differential executable codes and shared executable codes.

Description

technical field [0001] Embodiments of the present disclosure relate to the technical field of processors, and more specifically, to a code generation / execution method, device, device, and storage medium. Background technique [0002] For processors, it is generally necessary to support two or more execution modes. For example, for graphics processing units (graphics processing unit, GPU), domain-specific software architecture (Domain Specific Architecture, DSA) accelerators, or other types of processors, it is necessary to A set of instruction set architecture (InstructionSet Architecture, ISA) to support the above two or more execution modes. For the same user code, the compiler in the related art needs to generate two or more executable codes respectively corresponding to two or more execution modes for all user codes, so as to support the two or more execution modes. However, this implementation method will reduce the execution efficiency of the processor and affect the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/30G06F9/448
CPCG06F8/31G06F9/4482
Inventor 不公告发明人
Owner 北京壁仞科技开发有限公司
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