Chip package structure

Abstract

The invention provides a chip package structure including a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one via structure penetrating through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.

Description

technical field [0001] The present invention relates to a chip packaging structure, in particular to a chip packaging structure with multi-chip stacking. Background technique [0002] With the miniaturization and multi-functionalization of electronic products, multi-chip packaging structures are becoming more and more common in many electronic products. It is to package two or more chips in a single package structure to reduce the overall volume. In a common multi-chip packaging structure, more than two chips are arranged side by side on the same substrate, but the side-by-side arrangement of the chips will increase the area of ​​the packaging structure as the number of chips increases. To solve this problem, a stacking method is currently developed to configure chips. However, there are still disadvantages in the way of stacking chips, for example, stacking chips vertically will cause the package structure to be too thick, and the resistance of the chip stacked on the top ...

AI Technical Summary

Problems solved by technology

However, there are still disadvantages in the way of stacking chips. For example, stacking chips vertically will cause the thickness of the package structure to be too high, and the resistance of the chip stacked on the top to be electrically connected to the circuit board will become larger, which will increase power consumption.

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