Circuit for preventing latch of I/O port in power-on process of processor

Abstract

The invention relates to the technical field of latch resistance, in particular to a circuit for preventing latch of an I / O port in the power-on process of a processor. The circuit comprises a control unit, the processor, a power-on control switch, a grounding switch and a release switch. After the control unit is powered on, a first signal node, a second signal node, a third signal node and a fourth signal node output trigger signals in sequence; a trigger signal output by the first signal node enables the grounding switch to be kept on; a trigger signal output by the second signal node enables the power-on control switch to be kept on; a trigger signal output by the third signal node enables the processor to reset; and the trigger signal output by the fourth signal node enables the trigger end of the grounding switch to be in grounding short circuit, and the signal is released. According to the circuit, the level state of the I / O port end of the processor is lowered before the processor is started, so that the power-on starting and resetting of the processor are both carried out when the I / O port end is in the low level state, and the defect that the resetting function is abnormal due to the fact that the I / O port end of the processor is in the high level is overcome.

Description

technical field [0001] The invention relates to the technical field of latch-up resistance, in particular to a circuit for avoiding I / O port latch-up during power-on of a processor. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the use of processors is becoming more and more extensive, and the performance requirements of processors are becoming more and more stringent, especially in the circuit environment where multiple processors work together. [0003] In the prior art, the circuit structure in which multi-processors work together mainly includes a main processor, a processor and a power supply module, wherein the main processor and the processor realize data communication through an I / O port, and the enabling lead of the main processor The pin is connected to the power supply pin of the processor through the power supply module, thereby controlling the power supply module to power on the processor. However, sinc...

AI Technical Summary

Problems solved by technology

However, since the I / O port of the processor already has voltage when it is connected to the main processor, powering on the processor will easily cause some pins of the processor to enter the latch effect and cannot communicate normally, such as UART, I 2 C, SPI and other communication interfaces

Images