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Encryption and decryption operation acceleration method and system and storage medium

An encryption and decryption, encryption and decryption module technology, applied in the field of systems and storage media, encryption and decryption operation acceleration methods, can solve the problems of low efficiency of encryption and decryption operations

Active Publication Date: 2021-09-10
罗克佳华(重庆)科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the embodiment of this application is to provide an encryption and decryption operation acceleration method, system and storage medium, which are used to improve the relatively low efficiency of encryption and decryption operations

Method used

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  • Encryption and decryption operation acceleration method and system and storage medium
  • Encryption and decryption operation acceleration method and system and storage medium
  • Encryption and decryption operation acceleration method and system and storage medium

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Embodiment Construction

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0023] Before introducing the encryption and decryption operation acceleration method provided by the embodiment of this application, some concepts involved in the embodiment of this application are introduced first:

[0024] Field Programmable Gate Array (Field Programmable Gate Array, FPGA) is based on Programmable Array Logic (Programmable Array Logic, PAL), General Array Logic (Generic Array Logic, GAL), Complex Programmable Logic Device (Complex Programming Logic Device , CPLD) and other programmable logic devices based on technology developed technology. As a semi-custom circuit in special application integrated circuits, FPGA not only makes up for the shortage of fully customized circuits, but also overcomes the shortcomings of the limited number of gate circuits of t...

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Abstract

The invention provides an encryption and decryption operation acceleration method and system and a storage medium, which are used for solving the problem of relatively low efficiency of encryption and decryption operation. The method comprises the following steps: receiving a plurality of data fragments of a to-be-processed data packet through a first first-in first-out module, and sending the plurality of data fragments of the to-be-processed data packet to an encryption and decryption module; receiving a plurality of data fragments of a to-be-processed data packet through an encryption and decryption module, carrying out encryption and decryption parallel operation on the plurality of data fragments of the to-be-processed data packet to obtain operation result data of the plurality of data fragments, and then sending the operation result data of the plurality of data fragments to a second first-in first-out module; and receiving the operation result data of the plurality of data fragments through the second first-in first-out module, and caching the operation result data of the plurality of data fragments.

Description

technical field [0001] The present application relates to the technical field of computer security and network security, in particular, to an encryption and decryption operation acceleration method, system and storage medium. Background technique [0002] At present, the method of accelerating encryption and decryption operations is usually based on the buffer mechanism (Buffer Mechanism). Take the national secret SM4 algorithm that needs to calculate 32 rounds of calculations as an example. For example, first cache the data packets to be processed to the storage module , that is to use the storage module as a buffer, assuming that there are 3K data packets to be processed, do not do any processing when receiving and buffering 1K data, continue to receive and buffer; when receiving and buffering 2K data, do not do any processing, continue to receive and buffer. After the 3K data packets to be processed in the cache are all received, the data packets to be processed are extra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/60G06F13/40G06F5/06
CPCG06F21/602G06F13/4022G06F5/06G06F2213/0026
Inventor 李玮廖强夏博儒张俊峰楚梁陈维沈扬斯吴魁栾怀训谢晓民
Owner 罗克佳华(重庆)科技有限公司
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