Bus device, embedded system and system on chip

Abstract

The embodiment of the invention provides a bus device, an embedded system and a system on chip. The bus device comprises: a write command buffer for caching a plurality of write addresses sent by a master device, and transmitting continuous write addresses to the same slave device in the plurality of write addresses to an address redirection unit according to the notification of an arbitration unit; the address redirection unit which is used for redirecting the write address of the same slave device to the address space of the same slave device; and an arbitration unit which is used for notifying the write command buffer to transmit the write address after the write address of the same slave device after the write transaction of the write address of the same slave device is executed. According to the bus device provided by the embodiment of the invention, the continuous write transactions of the write addresses of the same slave equipment in the plurality of write addresses are executed firstly, and then the write transactions of the subsequent write addresses are executed, so that the problem of bus interlocking is avoided.

Description

technical field [0001] The present disclosure relates to the field of chips, and in particular, relates to a bus device, an embedded system and a system on a chip. Background technique [0002] With the continuous expansion of the system on chip (SoC), the bus structure and hierarchical relationship have also become extremely complicated, and the cascading of bus devices will inevitably appear in the design of large-scale system on chip. Bus interlock problems arise when design considerations are poor or when bus devices do not match the behavior of the devices. refer to figure 1 As shown, the master device 1 sends a read and write request to the slave device 1 through the path 1 of the bus device 1, forwards it to the bus device 0 through the path 2, and then loops back to the bus device 1 through the path 3. At this time, the path 2 and the path 3 form Loopback causes the system to fail to complete the read and write requests from master device 1 to slave device 1. Simi...

AI Technical Summary

Problems solved by technology

Although as figure 1 The typical interlock problems shown are relatively easy to find and correct at the early stage of design, but with the complexity of the bus device architecture, it becomes more difficult to find bus interlock problems, often in the large-scale stability test stage at the very end of the project , based on a very random stress test, it is only possible to find interlock problems in the bus device architecture with a small probability

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