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Chip and chip testing method

A chip and test circuit technology, applied in the test field, can solve the problems of occupying signal bump circuit space, waste, etc.

Active Publication Date: 2022-02-22
北京壁仞科技开发有限公司 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the transmitting end circuit of a traditional chip usually occupies a large area of ​​signal bumps, resulting in a waste of circuit space, and also has the influence of high parasitic capacitance

Method used

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  • Chip and chip testing method

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Embodiment Construction

[0041] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference symbols are used in the drawings and descriptions to refer to the same or like parts.

[0042] figure 1 is a schematic circuit diagram of the chip of the first embodiment of the present invention. refer to figure 1 , the chip 100 includes a sending circuit 110 and a testing circuit 120 . The testing circuit 120 can perform electrical testing on the transmitting end circuit 110 . In this embodiment, the sending end circuit 110 includes a signal sending unit 111 and signal bumps (signal bumps) 112 , 113 . The signal sending unit 111 may include a driver (Driver) circuit. The signal sending unit 111 is coupled to the signal bumps 112 , 113 . In some embodiments of the present invention, the transmitting end circuit 110 may include one or more signal bumps, not limited to figu...

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Abstract

The invention provides a chip and a chip testing method. The chip includes a sending end circuit and a test circuit. The sending end circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to the signal sending unit and the circuit node between the first signal bumps. The test circuit includes a first resistor, a unity gain buffer, and an analog-to-digital converter. The first end of the first resistor is coupled to the circuit node. The first input end of the unity gain buffer is coupled to the second end of the first resistor. The second input end of the unity gain buffer is coupled to the output end of the unity gain buffer. The input terminal of the analog-to-digital converter is coupled to the output terminal of the unity gain buffer. The chip and the chip testing method of the invention can realize an effective chip testing function.

Description

technical field [0001] The invention relates to a testing technology, in particular to a chip and a chip testing method. Background technique [0002] With the increase in the demand for the calculation of the chip, the requirements for the bandwidth and delay of the single-chip system (System on a Chip, SOC) and the speed of the sequencer / de-serializer (SERializer / DESerializer, SERDES) protocol are also increasing. come higher. In this regard, the sending end of the traditional chip must design a large-area signal bump to meet the requirements of Design for Testability (DFT) in the manufacturing process of high-speed chips, so that it can perform related electrical tests . Therefore, the transmitting end circuit of a traditional chip usually occupies a large area of ​​signal bumps, resulting in a waste of circuit space, and also has the influence of high parasitic capacitance. Contents of the invention [0003] The invention is aimed at a chip and a chip testing method...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28G01R31/52
CPCG01R31/2851G01R31/52G01R31/31715G01R31/3187G01R31/2884H01L22/34
Inventor 不公告发明人
Owner 北京壁仞科技开发有限公司