Direct bonded stack structures for increased reliability and improved yield in microelectronics

Abstract

Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to U.S. Nonprovisional Patent Application No. 16 / 911,360, filed June 24, 2020, and to Uzoh et al., U.S. Provisional Patent Application No. 62 / 866,965, filed June 26, 2019 of priority, the entire contents of which are incorporated herein by reference. Background technique [0003] During the fabrication of conventional 3DIC microelectronic packages such as high bandwidth memory modules (HBM, HBM2, HBM3), stacks of integrated circuit microchips (“die”) that are bonded together are susceptible to certain types of defects, and these defects affect the overall production yield. For example, in the case of HBM2 modules, the memory specification may dictate certain physical dimensions of the module to be built, such as a height requirement of 700pm. [0004] Such as figure 1 As shown, the high bandwidth of the example conventional HBM2 memory module 100 is achieved by bonding multiple memor...

AI Technical Summary

Problems solved by technology

When the upwardly recessed top die 106 is pressed into the downwardly recessed die stack 102 below it during bonding to the vertical stack 103, destructive defects, such as direct bond Cracks 114 of bonded die 102, post-bonding delamination 116 between die, or cracking and chipping 118 of substrate 104 below the vertical stack at points of increased stress, thereby reducing overall yield

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