Improved high-speed FPGA lookup table circuit

Abstract

The invention relates to an improved high-speed FPGA lookup table circuit, and the circuit is provided with a plurality of selection signal input ends and a plurality of signal output ends in sequence by arranging a fast decoding circuit; a first-stage phase inverter circuit which is provided with a plurality of configuration signal input ends and first-stage phase inverters respectively connected with the configuration signal input ends; a transmission tube circuit which is provided with a plurality of transmission tubes, wherein the transmission tubes are correspondingly connected with the primary inverters, and the transmission tubes are further connected with the signal output ends of the rapid decoding circuit; and an output circuit which is connected with a part of the transmission tubes in the transmission tube circuit so as to improve A-Q delay in the lookup table circuit.

Description

Technical field [0001] The present application relates to the field of FPGA technology, in particular to an improved high-speed FPGA lookup table circuit. Background technique [0002] FPGA is an integrated circuit that can implement any combined logic and timing logic functions according to configuration data, and the lookup table circuit is a core circuit that implements a combined logic function. The lookup table circuit is a circuit that is often used, such as figure 2 As shown, the commonly used lookup table circuit in the prior art is 4 input 16 selected 1 multiplexer, and the complex combination logic function can be realized when a large number of lookup table circuit combines, and when the lookup table is used, The latency of the lookup table circuit is one of the key to determining the speed of logical functions in FPGA. [0003] like figure 2 As shown, the latency of the lookup table circuit includes the P-Q delay of the selection signal A (A0-A3) to the output Q and t...

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Problems solved by technology

[0005] However, since the AND operation needs to be performed after inverting the selection signal A, for example, in the decoder circuit generating R2 such as image 3 As shown, in addition, the output stage I16 requires two stages of inverters, so its A-Q delay is 5Tc+2Ts. Since Tc and Ts are equivalent, compared with image 3 The circuit, the A-Q delay included in the technical solution of the invention patent with the application number 201310536697.X has no obvious improvement, or even worse, which is not effective in improving the running speed of the logic function implemented by the FPGA, which in turn leads to the improvement of the A-Q delay bad question

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