Simulation verification platform construction method, simulation verification method, simulation verification device and simulation verification equipment

Abstract

The embodiment of the invention provides a simulation verification platform construction method, a simulation verification method, a simulation verification device and simulation verification equipment. The simulation verification platform construction method comprises the following steps: determining conflict information among a plurality of subsystems to be tested; compiling the modules corresponding to the conflict information in the plurality of to-be-tested subsystems respectively, and configuring the modules to different compiling libraries, so that the modules in the same to-be-tested subsystem are correspondingly configured to the same compiling library; a joint simulation environment is constructed, the joint simulation environment comprises a top-layer simulation environment and a plurality of instance subsystems contained in the top-layer simulation environment, and the instance subsystems are obtained based on instantiation of the to-be-tested subsystems; wherein the compiling library corresponding to one to-be-tested subsystem is only called by the instance subsystem corresponding to the to-be-tested subsystem, so that wrong calling during simulation verification of a plurality of to-be-tested subsystems can be avoided, and system-level joint verification of a plurality of subsystem chips is realized.

Description

technical field [0001] The embodiments of the present invention relate to the field of chip technology, and in particular to a method for building a simulation verification platform, a simulation verification method, a device, and equipment. Background technique [0002] Chip verification is used to verify whether the chip design meets the requirements specifications defined by the chip based on the corresponding verification environment before chip production, whether it contains design defects, and correct them in time after defects are found. [0003] With the rapid development of the integrated circuit industry, the scale of the chip has greatly increased, which makes the simulation verification of the chip more and more complicated and difficult to achieve. For this reason, for ultra-large-scale SoCs, they are usually divided into multiple subsystem chips to be verified separately. After the verification of each subsystem chip is completed, only simple system-level join...

AI Technical Summary

Problems solved by technology

[0003] With the rapid development of the integrated circuit industry, the scale of the chip has increased greatly, which makes the simulation verification of the chip more and more complicated and difficult to achieve.

For this reason, for ultra-large-scale system-level chips, it is usually divided into multiple subsystem chips to be verified separately. After the verification of each subsystem chip is completed, only simple system-level joint debugging of the subsystem chips can be performed through the hardware platform.

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