Phase estimating circuit and demodulating circuit
A circuit and phase technology, applied in electrical components, phase-modulated carrier systems, digital transmission systems, etc., can solve the problems that the phase of the clock signal is easily affected by noise and the output value of the low-pass filter is small
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 example
[0047] In the following, the embodiment is the same as the original example, the Fourier transform adopts DFT, and the case where the number of samples per symbol N=4 will be described. Normally, the received signal is subjected to nonlinear processing to facilitate extraction of the clock component from the input signal of the clock regeneration circuit, but the presence or absence of the nonlinear processing circuit has no influence on the invention described below. Therefore, the description of the nonlinear processing circuit is omitted below, and it is simply referred to as the input signal. Since noise removal filters generally use averaging filters, they all appear in the form of averaging filters in the following embodiments.
[0048] figure 1 is a block diagram of a phase estimation circuit according to an embodiment of the present invention. figure 2 is a flowchart of the operation of the phase estimating circuit according to the first embodiment of the present i...
no. 2 example
[0065] image 3 is a block diagram of a phase estimating circuit according to a second embodiment of the present invention. Figure 4 is a flowchart of the operation of the phase estimating circuit according to the second embodiment of the present invention. exist image 3 Among them, 10 is a pattern detection circuit, and when a desired pattern is detected in the output of the DFT circuit 31, the operation of the averaging filter 32 is stopped. The input terminal 1, the signal generating circuit 9, the DFT circuit 31, the averaging filter 32, the output terminal 51, and the output terminal 52 are all the same as those described in the first embodiment, so their descriptions are omitted.
[0066] Refer below image 3 and Figure 4 Describe its action.
[0067] The DFT circuit 31 calculates the DFT ( Figure 4 step 201). The pattern detection circuit 10 detects the clock signal component ( Figure 4 step 105). The averaging filter 32 outputs phase information. Here, a...
no. 3 example
[0077] Figure 5 is a block diagram of a phase estimating circuit according to a third embodiment of the present invention. Figure 6 is a flowchart of the operation of the phase estimation circuit according to the third embodiment of the present invention.
[0078] exist Figure 5 Among them, 12 is a phase detection circuit, and the output of the averaging filter 32 is used to obtain the phase of the clock signal.
[0079] 11 is a pattern detection circuit, which uses the DFT result output from the DFT circuit 31 and the phase information output from the phase detection circuit 12, and stops the operation of the averaging filter 32 when there is a pattern capable of reducing the clock signal component.
[0080] The input terminal 1, the signal generating circuit 9, the output terminal 51, the output terminal 52, the DFT circuit 31, and the averaging filter 32 are all the same as those described in the first embodiment.
[0081] use below Figure 5 and Figure 6 Describe it...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More