Distributing ECC bits to allocate ECC bits for metadata

Abstract

The present disclosure generally relates to distributing ECC bits to allocate ECC bits for metadata. The memory subsystem includes a plurality of memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem may divide a portion of data into a plurality of sub-portions. Segmentation into smaller portions requires fewer ECC (Error Check and Correction) bits to provide the same level of ECC protection. The portion of data may include N ECC bits for error correction, and each sub-portion may include a sub-portion of (N-M) ECC bits for error correction. The system may then use M bits of data for non-ECC purposes, such as metadata.

Description

technical field [0001] The description relates generally to memory systems and, more particularly, to data storage and system management of error correction bits. Background technique [0002] Increasing memory device densities and operating speeds, combined with smaller feature sizes of memory device manufacturing processes, tend to lead to an increase in runtime errors for memory devices. Memory systems employ error checking and correction (ECC) to correct errors that might otherwise lead to system failure. DRAM (dynamic random access memory) devices are often used in modules such as DIMMs (dualinline memory modules), which include multiple DRAM devices connected in parallel . Memory systems using DIMMs are often expected to provide single device data correction (SDDC), where failures of the entire DRAM device of the DIMM can be corrected. [0003] Upcoming memory device standards anticipate more internal prefetching and longer burst lengths to result in greater data ba...

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Problems solved by technology

[0003] Upcoming memory device standards anticipate more internal prefetching and longer burst lengths to result in greater data bandwidth per memory device access transaction (e.g., read or write)

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