Pictrue signal shffling device and method

[0108] (Example 1)

[0109] figure 1 It is a block diagram of the image signal shuffling device of Embodiment 1 of the present invention.

[0110] in figure 1 , The digital image signal input from the input terminal 10 is input to the memory 18.

[0111] The block address generating unit 13 generates addresses for dividing the input data into blocks on the memory. The arrangement change address generating unit 14 generates an address for changing the arrangement of the blocks on the memory.

[0112] The memory write control unit 12 controls the block address generation unit 13 and the arrangement change address generation unit 14 to calculate a unique address on the memory based on the position of the input data on the screen and write the input data to the specified address.

[0113] The memory read controller 15 reads out the data on the memory 18 and outputs it to the designated channel by using the segment address generating unit 16 that generates segments based on the data on the memory 18 and the channel address generating unit 17 that generates channel addresses of output segments.

[0114] figure 2 It is a diagram explaining the writing to the memory in the first embodiment. The following describes the case where the input signals of the number of horizontal pixels Xp and the number of vertical lines Yp are written into the memory area of ​​the number of horizontal pixels Ap (Ap>Xp) and the number of vertical lines Bp (Bp>Yp) (here, let Xp×Yp= Ap×Bp).

[0115] in figure 2 Here, the solid line represents the pixel area of ​​the input signal, and the broken line represents the area of ​​the memory 18. When the screen and the memory are in one-to-one correspondence, it cannot be directly written into the memory. Therefore, the arrangement change address generating unit 14 generates an area of ​​(Ap-Xp)×Bp that moves the Xp×(Yp-Bp) area on the screen to the memory. The address where the area is written.

[0116] In addition, the movement processes such as the above-mentioned arrangement change and segment formation are all performed with a block as the minimum unit.

[0117] Now, suppose that the block is composed of horizontal Kp pixels×vertical Kp lines. Here, when the vertical Yp line is in the relationship of Yp=Kp×Lp (Lp is a natural number)+Kp/2 with respect to the Kp of the smallest unit of the block, the block address generating unit 13 generates a horizontal (2 ×Kp) pixel × vertical (Kp/2) row block write address to the memory.

[0118] The memory read controller 15 uses two types of address generating units, the segment address generating unit 16 and the channel address generating unit 17, to read from the memory. To generate the read address from the memory, first, the segment address generating unit 16 generates an address corresponding to the number of the segment to be output to the channel. It is performed by a simple method of calculating the offset value of each channel generated by the channel address generating unit 17 in the horizontal and vertical directions to the address.

[0119] This is because when the segments are formed, the read addresses of the blocks on the memory located far away from each other on the screen have the same offset value in the horizontal and vertical directions regardless of the channel, and they are different in each channel. , Is just the address on the memory at the beginning.

[0120] According to the read address determined in the above-mentioned manner, a segment is formed by reading a plurality of blocks.

[0121] In addition, the address of the block, the address of the arrangement change, the segment address, and the channel address are arbitrary.

[0122] (Example 2)

[0123] image 3 It is a block diagram of the image signal shuffling device of the second embodiment of the present invention.

[0124] in image 3 Middle, for and figure 1 Blocks with the same actions are marked with the same symbols, and their descriptions are omitted.

[0125] in image 3 , The image signal input from the input terminal 10 is output to the format converter 11.

[0126] The format converter 11 limits the frequency band of the input signal and simultaneously converts the number of pixels of the input signal.

[0127] Here, it is assumed that the input signal is a signal in which the number of horizontal pixels is Mp and the number of vertical lines is Np.

[0128] Here, it is assumed that Mp and Np are in the relationship of Mp≥Xp and Np≥Yp with respect to the number of horizontal pixels Xp and the number of vertical lines Yp of the input signal.

[0129] The format converter 11 limits the frequency band of the input pixels and then thins the pixels, thereby converting the input signal into a signal of the number of horizontal pixels Xp and the number of vertical lines Yp, and outputs the signal to the memory 18.

[0130] As described above, the image signal shuffling device of the second embodiment adds a format converter to the first embodiment to make the input signal in a format consistent with the shuffled pattern, so that it can correspond to signals of many specifications.

[0131] The format conversion can be only in the horizontal direction or the vertical direction, and it is also possible to reduce the pixels without limiting the frequency band. In short, it is sufficient to perform the conversion so that the number of input pixels matches the number of shuffled pixels.

[0132] (Example 3)

[0133] Figure 4 It is a diagram for explaining the third embodiment of the present invention.

[0134] The block diagram of the image signal shuffling device of this embodiment and image 3 the same.

[0135] Below, use image 3 with Figure 4 The operation of the image signal shuffling device of this embodiment will be described.

[0136] The number of effective lines is 1080 lines, the number of effective pixels in the horizontal direction (the number of effective pixels per line) of the luminance signal (hereinafter referred to as Y signal) is 1920 pixels, and 2 color difference signals (hereinafter referred to as Cr and Cb respectively) Signal), the number of effective pixels in the horizontal direction is 960 pixels for the image signal (see Figure 4 (a)) Input to terminal 10.

[0137] The format converter 11 limits the frequency band of the input signal, converts the number of horizontal pixels of the Y signal to 1280 pixels, and converts the number of horizontal pixels of the Cr and Cb signals to 640 pixels (see Figure 4 (b)). The block address generation unit 13 generates a block address for the area 1 of 1072 lines within the effective number of 1080 lines. The Y signal uses a horizontal 16 pixels × vertical 16 line block to generate a block address, and the Cr and Cb signals use a horizontal 8 pixel × vertical 16 line block. The block generates a block address.

[0138] For the area 2 of the remaining 8 rows, the Y signal uses a horizontal 32 pixels × vertical 8 row block to generate a block address, and the Cr and Cb signals use a horizontal 16 pixel × vertical 8 row block to generate a block address.

[0139] in Figure 4 In (c), in order to easily understand the relationship with the pixels, it means using the blocks of area 2 and figure 1 The block is divided into blocks of the same block size.

[0140] On the screen, take a Y signal block and Cr and Cb signal blocks at the same position as a macro block (hereinafter, the table is MB), such as Figure 4 As shown in (d), the arrangement is changed to 90MB in the horizontal direction and 60MB in the vertical direction.

[0141] Figure 5 It is a diagram for explaining the change in the arrangement of blocks in this embodiment.

[0142] Such as Figure 5 As shown, for the vertical 60MB in the center, the arrangement is not changed, and the upper and lower parts are changed and arranged to the right end.

[0143] The upper area of ​​80MB in the horizontal direction and 4MB in the vertical direction is divided into 8 areas from U0 to U7 with a unit of 10MB in the horizontal direction.

[0144] The arrangement change does not change the MB arrangement in the area, but only moves. As a result, it becomes an area of ​​10MB horizontally and 32MB vertically.

[0145]The lower area of ​​80MB horizontally and 3MB vertically, as in the upper case, the area of ​​D0-D7 moves as indicated by the arrows, and becomes an area of ​​10MB in the horizontal direction and 24MB in the vertical direction. The remaining D8 area of ​​40 MB in the horizontal direction and 1 MB in the vertical direction is also divided into 4 areas of 10 MB in the horizontal direction and moved to become an area of ​​10 MB in the horizontal direction and 4 MB in the vertical direction.

[0146] As described above, the horizontal direction 90MB × vertical direction 60MB (see Figure 4 The area of ​​(d)) is divided in units of 1MB in the vertical direction, such as Figure 4 As shown in (e), it is divided into two areas of 90 MB in the horizontal direction and 30 MB in the vertical direction (Ns=30). In addition, these two regions are divided into 90 MB in units of 9 MB in the horizontal direction. By using this horizontal direction to form 1 area per 9MB area, 4 areas are formed (see Figure 4 (e)). In other words, four regions composed of macro blocks of 45 MB in the horizontal direction (Ms=45) and 30 MB in the vertical direction (Ns=30) are formed.

[0147] In this embodiment, take Lh=5, Lv=5, in Figure 4 The broken line in (e) constitutes 9MB in the horizontal direction (Ms/Lh=9) and 6MB in the vertical direction (Ns/Lv=6).

[0148] These 4 areas correspond to the 4 output channels A, B, C, and D.

[0149] Figure 4 The small squares in (e) indicate the blocks where the reading of each channel is started.

[0150] As shown in the figure, according to the read addresses at different start positions for each of the four areas, five blocks having the same value in the horizontal and vertical directions in all areas are combined to form a segment.

[0151] The formation of such segments is repeatedly moved in the vertical and horizontal directions to form a segment of one frame.

[0152] The offset values ​​of the other MBs relative to the position of one MB of the five MBs forming the segment conform to the relationship of equations (1) and (2).

[0153] Hoff=MOD(k×Ms/Lh, Ms) (1)

[0154] Voff=MOD(p×k×Ns/Lv, Ns) (2)

[0155] MOD(p, Lv)≠0, and MOD(Lv,p)≠0.

[0156] k=1, 2,..., Lh-1

[0157] Among them, MOD(a,b)=a-b×INT(a/b)

[0158] (a, b are integers, INT(a/b) is a function below the decimal point of the operation result of discarding independent variables)

[0159] In this embodiment, the value of p is 3, and the specific offset value is the nth (a positive integer) as (9, 18), (18, 6), (27, 24), (36, 12) The horizontal and vertical positions Hn and Vn of the first block of each segment conform to the relationship of equations (3) and (4).

[0160] Hn=MOD(H1+INT((n-1)/Lv), Ms/Lh) (3)

[0161] Vn=MOD(V1+Ns/Lv×MOD(n-1, Lv)

[0162] +INT((n-1)/Lv/(Ms/Lh)), Ns) (4)

[0163] Among them, H1 and V1 are the horizontal and vertical positions of the first block.

[0164] In this embodiment, (Ms/Lh×Ns)=270 segments are formed in one area.

[0165] Specifically, in Figure 4 In (e), within 9MB of 1 line of broken lines in the horizontal direction and 30MB of 5 lines of broken lines in the vertical direction,

[0166] In step 1: Scan every 6MB in the vertical direction

[0167] In step 2: every 5 scans in the vertical direction, move 1MB in the horizontal direction, and perform step 1

[0168] In step 3: every 45 scans, move 1MB in the vertical direction

[0169] Repeat steps 1, 2, and 3 to form 270 segments.