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Data processing device

A data processing device and data technology, which is applied in the direction of electrical digital data processing, register device, machine execution device, etc., can solve the problems of busy and bad developers, etc.

Inactive Publication Date: 2007-03-28
GK BRIDGE 1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The design modification procedure will be busy to the developer, and the development of the data processing device for media processing may also have a long-term tendency

Method used

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Experimental program
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no. 1 Embodiment

[0091] The data processing apparatus of the first embodiment is configured as shown in FIG. 1 to process a matrix composed of 16 elements in the vertical direction and 16 elements in the horizontal direction. FIG. 1 is a diagram showing a schematic configuration of a data processing device according to a first embodiment. The data processing device is composed of PE0 to PE15 of the same number as the number of elements in the horizontal direction of the matrix. Each PE includes an arithmetic operation unit (hereinafter referred to as ALU) and a register file (hereinafter referred to as RF). The arithmetic unit in each PE and the register file in each PE are connected to the network unit 20 .

[0092] The ALUs in the 16 PEs execute operations using the elements stored in the RF as operators. There is an ALU for each of the 16 PEs, so 16 operations are performed in parallel.

[0093] The RF in each PE includes the same number of registers r0 to 15 as the number of vertical el...

no. 2 Embodiment

[0110] This embodiment relates to an improvement when a data processing device is used in two applications of motion compensation and filter processing.

[0111] Describes the internal structure of the ALU when motion compensation and filter processing are performed. The ALU in this embodiment uses the four data inputted to the four input ports A, B, C, and D as operators A, B, C, and D to perform the operation of the operator A+. 7 is a diagram showing the internal structure of the ALU of this embodiment. As shown in the figure, the ALU includes an adder 23 that adds operator C and operator D, and multiplies operator B by the addition result (operator The multiplier 24 of C+operator D) adds operator A to the multiplication result operator B×(operator C+operator D) and obtains the addition result operator A+operator B×(operator C+operator D ) accumulator. The constituent elements having an addition function in this specification are not limited to addition processing, and ma...

no. 3 Embodiment

[0143] This embodiment discloses how to realize the control of reading out pixels at a certain interval when implementing motion compensation and filter processing. FIG. 23 is a diagram showing the internal structure of the data processing device of this embodiment. The feature in this figure is that the differential adder (DDA) 26 is placed in the ALU of P0. The DDA 26 is provided on all of PE0 to PE15 and is connected not only to the first system selector 21 but also to the second system selector 22 . However, for the sake of simplification, the DDA26 in PE0 is used as the object in the following description.

[0144] DDA26 controls the network unit 20 so that when the element data[s] in the sth column of the matrix is ​​passed and the certain interval is α, the variable s is changed by s←s+α operation and the element data[s] is output with the certain interval as a difference. to the ALU. Since the element data[s] in the sth column of the matrix is ​​stored in the RF...

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Abstract

A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

Description

technical field [0001] The present invention relates to a data processing device, and relates to an improvement for efficiently performing media processing such as decoding processing of image data and audio data, and demodulation processing of communication data. Background technique [0002] In media processing such as decoding processing of image data and audio data, and demodulation processing of communication data, there are many opportunities to process matrix-like data arranged two-dimensionally in N×M. In order to process the data matrix at high speed, there is a tendency to adopt a parallel architecture suitable for processing a plurality of data in a data processing device for media processing. Generally, high-speed processing of a data matrix is ​​realized by increasing the number of processing elements (hereinafter referred to as PEs). The so-called PE is an extended unit of hardware including an arithmetic unit, registers for supplying data to the arithmetic un...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/16G06F15/80G05B19/18G06F9/30G06F9/38
CPCG06F9/3824G06F9/3012G06F9/30036G06F9/3885
Inventor 森下广之伊藤敦高岛敏西田英志木村浩三清原督三三好明廉田浩
Owner GK BRIDGE 1