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Method for forming power devices and structure thereof

A power device and power technology, applied in the field of forming semiconductor devices, can solve problems such as heat dissipation, increased transistor power dissipation, slow rise and fall time, etc.

Inactive Publication Date: 2004-04-07
SEMICON COMPONENTS IND LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Another issue is heat dissipation and power loss
Difficulty turning the transistor on and off results in slow rise and fall times which will increase the power dissipation of the transistor
[0005] Also, it's hard to keep the power tubes off

Method used

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  • Method for forming power devices and structure thereof
  • Method for forming power devices and structure thereof
  • Method for forming power devices and structure thereof

Examples

Experimental program
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Embodiment Construction

[0014] This description includes a method of forming a power device that, along with other features, has reduced turn-on and turn-off times, increased immunity to instantaneous turn-off states, and predictable timing.

[0015] figure 1 This schematically shows a part of the power device 10 of an embodiment. The device 10 includes a power MOSFET 11 formed on a semiconductor die. The device 10 also includes a driving circuit 12 formed on an independent semiconductor die and connected to the driving power MOSFET 11. In the preferred embodiment, the power MOSFET 11 and the driving circuit 12 are attached to a lead frame and packaged in the same semiconductor housing. In another embodiment, the driving circuit 12 and the power MOSFET 11 may be formed in different package configurations including independent packages.

[0016] The power MOSFET 11 includes a power tube 27 and a pull-down transistor 28. The power MOSFET 11 is typically a large semiconductor device and is generally forme...

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PUM

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Abstract

A method of forming a power device (10) includes forming a power transistor (27) and a pull-down transistor (28) on a semiconductor die (36). The pull-down transistor (28) is enabled to rapidly and predictably disable the power transistor (27). The pull-down transistor (28) remains enabled for a first time period during the enabling of the power transistor (27) to facilitate rapidly and predictably enabling the power transistor (27).

Description

Technical field [0001] The present invention relates generally to electronics, and more specifically to methods and structures for forming semiconductor devices. Background technique [0002] In the past, the semiconductor industry used multiple technologies to control metal oxide semiconductor (MOS) power transistors. A typical MOS power tube is very large and dissipates a large amount of power, so the MOS power tube is generally formed on a single semiconductor die. Typically, this power tube is driven by a semiconductor device external to the power tube. The driving transistor is typically a small MOS transistor connected to a totem pole structure to provide active pull-up and pull-down of the gate of the power tube. [0003] One problem with this method and device is inaccurate timing prediction. MOS power transistors typically have large gate capacitance and large inductance due to the bond wires connecting the gate to the external pins. Because of this capacitance and induc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/0412
CPCH03K17/04123
Inventor 本杰明·M.·赖斯
Owner SEMICON COMPONENTS IND LLC