Method for determining a reference pulse phase from band-limited digital data streams

A technology of reference clock and data stream, applied in digital transmission systems, electrical components, transmission systems, etc., can solve problems such as increasing phase jitter and deteriorating effective signals

Inactive Publication Date: 2004-06-23
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] The disadvantage of this conventional approach is that bit-pattern-dependent distortions must be avoided, and as a result, the spectrum of the data stream must also contain frequency components above the central frequency of the useful signal
[0010] This creates additional disadvantages: noise components are also transmitted and amplified, which degrades the effective signal and increases phase jitter
[0012] Furthermore, disturbances such as jitter, i.e. common noise, band limitation due to the transmission channel, etc. have an adverse effect on the determination of the reference clock phase RT, therefore, there is a large error in such conventional determination methods

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  • Method for determining a reference pulse phase from band-limited digital data streams
  • Method for determining a reference pulse phase from band-limited digital data streams
  • Method for determining a reference pulse phase from band-limited digital data streams

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Embodiment Construction

[0036] figure 1 Shows eye diagrams of band-limited digital data streams with single-step and double-step data conversion.

[0037] in figure 1 In the eye diagram shown, you can see the digital data flow. For example, the figure shows data conversion. The data conversion represents a single step 0 / 1 data conversion 101, a single step 0 / -1 data conversion 103, and a single Step 1 / 0 data conversion 103a, single step 1 / 0 data conversion 101a, double step-1 / 1 data conversion 102, and double step 1 / 1 data conversion 104.

[0038] For example, the data conversion is represented as the conversion between the baseline value 105 and the maximum data flow value 106 or the minimum data flow value 107, or the conversion between the minimum data flow value 107 and the maximum data flow value 106, respectively. The variably adjustable threshold 108 and the data conversion have different intersections. For example, two intersections are shown, as the intersection of the 0 / 1 data conversion 101...

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Abstract

The invention provides a method for recovering a digital datastream (301), in which a reference clock phase (308) is recovered from the digital datastream (301), the digital datastream (301) being received in a datastream receiver (302), low-pass filtered in a low-pass filter device (303), an edge position signal (309) being determined by comparing an amplitude of the low-pass filtered datastream (305) with a predeterminable threshold value (108) in an edge position detection device (304) and a phase deviation (111a) being determined from a time difference between a 0 / 1 threshold intersection point (109) of the threshold value (108) with a 0 / 1 data transition (101) or a -1 / 1 threshold intersection point (110) of the threshold value (108) with a -1 / 1 data transmission (102) and the target time of the control system (310) in a phase correction device (307), so that the phase deviation (111a) can be corrected with the phase correction offset (111b) in the phase correction device (307).

Description

Technical field [0001] The present invention relates to a method of recovering a digital data stream, and more specifically, the present invention relates to a method of recovering a reference clock phase from a digital data stream. Background technique [0002] For example, the data stream is transmitted as an AMI (Signal Alternate Inversion) data stream. In the AMI data transmission method, the two lines do not have a DC (direct current) component in order to transmit the data stream, and the analog signal on one line is reversed with respect to the analog signal on the other line. [0003] In the following, a logic signal is a signal whose signal level changes from one logic state to another logic state, and it can be assumed that these signals have a minimum data flow value, a baseline value, or a maximum data flow value. In this structure, the smallest data flow value is called logic "-1", the baseline value is called logic "0", and the largest data flow value is logic "+1"....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/033
CPCH04L7/033
Inventor 托马斯·杜达托尔斯滕·欣茨马丁·伦纳
Owner INFINEON TECH AG
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