Semiconductor memory circuit

Abstract

Data reading speed of a DRAM is enhanced without causing an increase in the power consumption and in the chip area. To that end, when data is read, a pair of bit lines is precharged to a GND level, while a dummy cell is charged at a power supply voltage. Immediately after a word line and a dummy word line are activated and their respective potentials are increased by the threshold voltage of an access transistor, a main capacitor and a dummy capacitor are electrically connected to the bit lines, thereby allowing the data to fade in. The resultant potential difference between the pair of bit lines is detected and amplified by a sense amplifier, thereby enabling the data to be read. The capacitance of the dummy capacitor is about half of that of the main capacitor, so that the dummy capacitor can be precharged at the power supply voltage.

Description

technical field [0001] The invention relates to a semiconductor memory circuit, in particular to a memory access technology of a dynamic memory. Background technique [0002] Even among semiconductor memory circuits, dynamic random access memory (hereinafter referred to as DRAM) is often used as a device capable of reading and writing large amounts of data. Figure 12 Shows the circuit structure of a general DRAM currently in practical use. The DRAM 100 shown in the figure includes a memory cell 101 , a sense amplifier 102 and a precharge circuit 103 . Below, refer to Figure 13 The operation of DRAM 100 at the time of data reading will be described with a timing chart of FIG. [0003] First, when the memory cell 101 is inactive (WL="L"), the precharge circuit 103 is activated (PRE="H"), a pair of bit lines BL and BLX (hereinafter expressed as [bit line pair BL, BLX]) It is precharged to the voltage VDD / 2 (VDD is the power supply voltage). Thereafter, when the precharge ...

AI Technical Summary

Problems solved by technology

In terms of fine processing, since only the storage node part of the dummy cell 304 is connected to the precharge transistor 342, it is difficult to optimize the manufacturing process if it is formed in a shape different from that of a normal memory cell.

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