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Multi-thread parallel processing sigma-delta ADC

A technology of digital conversion and delta-sigma, applied in the direction of analog-to-digital converter, analog-to-analog conversion, code conversion, etc., can solve the problems of high-order delta-sigma ADC difficulties and instability

Active Publication Date: 2005-12-14
REALTEK SEMICON CORP
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AI Technical Summary

Problems solved by technology

Traditionally, the maximum operating frequency of the components that form the ADC delta-sigma modulator limits the maximum sampling frequency of the ADC, so a higher order ADC must be used to achieve higher resolution
However, it is quite difficult to design a stable high-order delta-sigma ADC due to the instability caused by multiple feedback loops

Method used

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Embodiment Construction

[0051] The detailed content of the description is an example of the best mode of the present invention for illustration, but the present invention is not limited to the following example or its operation mode.

[0052] FIG. 4 is a block diagram of a delta-sigma ADC according to a preferred embodiment of the present invention. The delta-sigma ADC30 is used to generate a representative analog input signal V IN The time-varying behavior of the digital output sequence s k . ADC30 includes S / H circuit 31, according to the clock edge of sampling clock signal CLK1, and with much higher than V IN bandwidth sampling rate periodically on the input signal V IN samples to produce a sequence of discrete analog samples x n . Serial / parallel (Serial / parallel, S / P) converter 32 is to deinterleave sampling sequence x n (n=(1,2,...,}), to form two analog sampling sequences x 2m+1 and x 2m , where x 2m+1 is given by the sequence x n All elements in which n is an odd number, and x 2m T...

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Abstract

Digitization of an analog input signal involves sampling the analog signal to produce a first sequence of analog samples representing continuous amplitudes, and deinterleaving the first sequence to form two or more second sequences. The second sequence is processed using a parallel processing delta-sigma modulator to generate two or more digital data elements of the third sequence. The third sequence is then interleaved to produce a fourth sequence of digital data elements. Finally, the fourth sequence is filtered and truncated to generate a fifth sequence of digital data elements representing the continuous amplitude of the analog input signal.

Description

technical field [0001] The present invention relates to an analog / digital converter, and in particular to a Sigma-delta analog / digital converter. Background technique [0002] A delta-sigma ADC is the use of an inexpensive and lower-resolution ADC to digitize an analog signal with a higher resolution. FIG. 1 is a schematic block diagram of an existing delta-sigma ADC. The delta-sigma ADC1 is used to generate a representative analog input signal V IN The digital output sequence s k . ADC1 includes a sample-and-hold (S / H) circuit 2 , a delta-sigma modulator 3 and a decimator (Decimator) 4 . S / H circuit 2 is based on the clock signal CLK1 to V IN The signal is sampled to produce a sequence of analog discrete samples x n . CLK1 signal frequency is much larger than the analog signal bandwidth, so V IN In essence, there will be oversampling (Over Sampling) phenomenon. The delta-sigma modulator 3 converts the analog sampling sequence x according to the timing of the CLK1 s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12H03M3/00
CPCH03M3/42H03M3/47
Inventor 林嘉亮
Owner REALTEK SEMICON CORP
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