Seal ring structure for integrated circuit chips

Abstract

This invention provides one sealed ring structure, semi-conductor crystal cycle and its method to arouse stress impact, wherein, the structure is suitable for one integration circuit chip core circuit area and comprises the following parts: one metal layer with one bridge layer and one bolt layer, one bridge connection part located the bridge layer between the integration circuit chip periphery and one certain position of the core circuit area; one bolt located in bolt layer aligning to bridge, wherein, the bolt has one width near to bridge. The said sealed ring structure and semi-conductor circle and the method limit crack progression on periphery.

Description

technical field [0001] The present invention relates to the design of semiconductor integrated circuit chips, and more particularly to a sealing ring structure (sealing ring structure), which has sufficient physical strength to limit and prevent the formation of corners and edges of integrated circuit chips. advance of the crack. Background technique [0002] Integrated circuit chips are manufactured in a rectangular array on a circular single crystal wafer. Most wafers are formed from silicon. Wafers can be divided by scribing, breaking, stress breaking or most commonly sawing. The separation line is aligned with the selected crystal axis, so that the separation of the wafers can be performed in a sequence and in a predetermined manner. However, this separation procedure still inevitably results in unintentional stress cracks. Such cracks occur at most near the corners of the integrated circuit chip where two perpendicular dividing lines intersect. Such fractures also ...

AI Technical Summary

Problems solved by technology

[0007] Therefore, the plugs in the existing sealing ring structure need to be better designed to limit and prevent the advancement of cracks from the edge of the integrated circuit chip

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