Seal ring structure, semiconductor wafer, and method for reducing stress effect due to cutting

Abstract

A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

Description

technical field [0001] The present invention relates to the design of semiconductor integrated circuit chips, and more particularly to a sealing ring structure (sealing ring structure), which has sufficient physical strength to limit and prevent the formation of corners and edges of integrated circuit chips. advance of the crack. Background technique [0002] Integrated circuit chips are manufactured in a rectangular array on a circular single crystal wafer. Most wafers are formed from silicon. Wafers can be divided by scribing, breaking, stress breaking or most commonly sawing. The separation line is aligned with the selected crystal axis, so that the separation of the wafers can be performed in a sequence and in a predetermined manner. However, this separation procedure still inevitably results in unintentional stress cracks. Such cracks occur at most near the corners of the integrated circuit chip where two perpendicular dividing lines intersect. Such fractures also ...

AI Technical Summary

Problems solved by technology

[0007] Therefore, the plugs in the existing sealing ring structure need to be better designed to limit and prevent the advancement of cracks from the edge of the integrated circuit chip

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