Method and data processor for reduced pipeline stalling

Abstract

A data processor (200) has a pipelined execution unit (120). Whether a first instruction is one of a class of instructions wherein as a result of execution of the first instruction the contents of an operand register will be stored in a destination register is determined. A second instruction that references the destination register is received before a completion of execution of the first instruction. The second instruction is executed using the contents of the operand register without stalling the second instruction in the pipelined execution unit (120).

Description

technical field [0001] The present invention relates generally to data processors and, in particular, to pipelined data processors. Background technique [0002] Some data processors use a technique called pipelining to increase performance. Pipeline processing technology is a kind of instruction processing task is divided into several smaller modular sub-tasks (modular sub-tasks), and each sub-task can be executed in a specific period of time called pipeline cycle (pipeline cycle). task technology. By dividing the task into these smaller cycles, a data processor can, for example, fetch one instruction while executing another instruction and writing the result of a third instruction back to the register file. Thus, the overall instruction execution rate approaches one instruction per pipeline cycle, even though individual instructions may take several cycles to complete. [0003] Modern microprocessors have more complex pipelines than the three-stage example. For example...

AI Technical Summary

Problems solved by technology

Also, some results are not available until the instruction reaches the end of the pipeline

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