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Method of implementation compensating dopant region and semiconductor device structure

A device structure and impurity region technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc.

Inactive Publication Date: 2006-08-30
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For SSRW devices based on gate length, the range of threshold voltage presents a challenge to fabricate devices with different dimensions

Method used

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  • Method of implementation compensating dopant region and semiconductor device structure
  • Method of implementation compensating dopant region and semiconductor device structure
  • Method of implementation compensating dopant region and semiconductor device structure

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Embodiment Construction

[0015] With reference to the accompanying drawings, image 3 The initial structure for realizing the method for compensating impurity regions according to the present invention is shown. As shown, a gate electrode 10 is provided comprising a spacer 12 surrounding a region of gate material 14 and a gate dielectric 16 . Gate electrode 10 is positioned over well 20 in substrate 22 . Also shown are source-drain regions 24, and base extension 26. In one embodiment, well 20 comprises a super-steep setback well as defined above. The type and amount of impurities in well 20 will vary depending on the type of device desired. For example, for an nFET, the impurity in well 20 is p-type. In one embodiment, the ultra-steep retrograde well 20 has an 3 impurity concentration, although this is not necessary.

[0016] Such as Figure 4 As shown in , the next step includes forming a planar dielectric layer 30 around the gate electrode 10 . The planar dielectric layer 30 can be made of s...

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Abstract

Methods and resulting structure of implementing a compensating implant that creates more compensation doping as the gate length is increased are disclosed. In particular, the invention performs an angled compensation implant through a gate opening during the damascene process such that the compensating dopant concentration increases as the gate length increases. In this fashion, the threshold voltage of a longer device is reduced much more than the threshold voltage of a shorter device, thereby reducing the threshold voltage of the longer device to acceptable levels without affecting the threshold voltage of the shorter device. The invention is especially advantageous relative to super-steep retrograde wells.

Description

technical field [0001] The present invention relates generally to semiconductor device fabrication, and more particularly to methods and resulting semiconductor device structures for realizing channel compensating impurity regions that produce more compensating doping as gate length increases. Background technique [0002] There is a continuing focus on reduction in threshold voltage in semiconductor device structures. A particular structure in which the threshold voltage is considered too high for long gate devices is the super steep setback well (SSRW) transistor device. The term "regression well" refers to a well formed using a method in which the highest (implanted) impurity concentration in the well is located at a distance from the surface, which makes the device less susceptible to breakdown. The term "supersteep" means that the transition from a lower impurity concentration to a higher concentration is rather abrupt, ie, the impurity profile is characterized by a su...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/265H01L29/78
CPCH01L21/26586H01L29/66537H01L21/268H01L29/66545
Inventor O·多库马奇
Owner INT BUSINESS MASCH CORP
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