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Method of converting a serial data stream to data lanes

A technology of serial data flow and data flow, which is applied in the direction of multiplexing communication, channel allocation device, time division multiplexing system, etc., and can solve problems such as ambiguity

Inactive Publication Date: 2006-09-13
ALCATEL LUCENT SAS
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

In addition, if the misalignment is greater than 32 bits, there is a possibility of blurring
Therefore, according to the prior art, only minor misalignments can be detected and corrected

Method used

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  • Method of converting a serial data stream to data lanes
  • Method of converting a serial data stream to data lanes
  • Method of converting a serial data stream to data lanes

Examples

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Embodiment Construction

[0019] figure 1 A general functional block diagram of SFI interface 1 is shown in . Interface 1 is the interface between SERDES component 2 , forward error correction (FEC) processor 3 and framer 4 . Data flow in the optics-to-system direction and data flow in the system-to-optics direction are represented by arrows 5 and 6, respectively. The data transmission between SERDES component 2 and FEC processor 3 and between FEC processor 3 and framer 4 is done through parallel signals RXDATA[3:0] (receive signal). Similarly, the data transmission in the reverse direction is completed through the parallel signal TXDATA[3:0] (send signal).

[0020] figure 2 A portion of the SFI interface, such as that implemented in SERDES component 2, is shown in . The incoming serial data stream is input into converter 10, where the serial data stream is demultiplexed into 4-bit lanes 11-14 of receive data bus 15 in a round-robin fashion. The channels 11-14 comprise data blocks of fixed length...

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Abstract

In a method of converting a serial data stream into a parallel data stream in a communications interface, wherein the serial data stream is demultiplexed to a given number of lanes (11 -14) and a sync header (24 - 27) is prepended to at least one data block (20 - 23) of at least one lane (11 - 14), for at least one lane (11 - 14) a sync word containing one or more bits, excluding the static word 01 as sync header, is given or generated and at least part of the sync word is used as sync header (24 - 27), which is prepended to the at least one data block (20 - 23). This allows for improved de-skewing.

Description

technical field [0001] The invention relates to a method for converting a serial data stream into a parallel data stream in a communication interface, wherein said serial data stream is demultiplexed into a given number of channels and is at least one data block of at least one data channel Presets a sync header. Background technique [0002] The SERDES Framer Interface (SFI) defines the connection between SONET / SDH framers (Synchronous Optical Network / Synchronous Digital Hierarchy framers) (or other devices such as forward error correction (FEC) processors) and high-speed parallel / serial The electrical interface between SERDES logic. The serial data received by the first chip is converted into a parallel data signal and transmitted to the second chip in parallel. The transmission lines between chips (which carry the data for each lane) may be of different lengths, so the transmission times between lanes may be different. The parallel data must be serialized again in the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04J3/16H04J3/06G06N99/00
CPCH04J3/0611H04L25/14
Inventor 贝特霍尔德·韦丁
Owner ALCATEL LUCENT SAS
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