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Time division multiplexing system minor node frame synchronization realizing method and apparatus

A technology of a time division multiplexing system and an implementation method, which is applied in the field of a time division multiplexing system sub-node frame synchronization implementation method and implementation device field, and can solve problems such as poor system fault tolerance performance and frame positioning errors

Active Publication Date: 2010-08-11
XFUSION DIGITAL TECH CO LTD
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Problems solved by technology

[0011] The present invention provides a sub-node frame synchronization implementation method and implementation device of a time division multiplexing system to solve the problems in the prior art that frame positioning errors are easily generated due to frame synchronization signal jitter and the system has poor fault tolerance performance

Method used

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  • Time division multiplexing system minor node frame synchronization realizing method and apparatus
  • Time division multiplexing system minor node frame synchronization realizing method and apparatus
  • Time division multiplexing system minor node frame synchronization realizing method and apparatus

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Embodiment Construction

[0043] Referring to Fig. 2, it is a sequence diagram of an embodiment of the first method for implementing frame synchronization of TDM system sub-nodes in the present invention. In the figure, the parent node of the TDM system sends a 32M (32.768MHz) clock, the frame frequency is 8KHz, and 3 cycles of low-level pulses The signal is a valid signal for frame synchronization, and assuming that one clock cycle (the second clock cycle) in the middle of the low level is the synchronization point as an example, the method for realizing frame synchronization of the sub-node is described as follows:

[0044] The frame synchronization arrival flag signal FSC_FLAG generates a valid signal in the second clock cycle of the low-level active cycle of the frame synchronization signal, and jumps from a low-level signal to a high-level signal (assuming that the main level is valid, and the low level is invalid), and its width is one clock cycle width.

[0045] The present invention adds a frame ...

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Abstract

A method for realizing subnode frame synchronization of TDM system includes adding function flag signal of frame synchronous regulation and applying it at counting of counter on subnode, detecting frame synchronous signal of father node when maximum value is achieved by subnode counter, setting said flag signal to be valid if it is high and setting flag signal to be invalid if it is low, resetting said counter and regulating local frame synchronization if said flag signal is valid or otherwise making counter count normally and holding local frame synchronization when frame synchronization arrival flag signal is valid.

Description

technical field [0001] The invention relates to the communication field, in particular to a method and device for realizing frame synchronization of sub-nodes of a Time Division Multiplexing (TDM) system. Background technique [0002] TDM technology is a channel sharing technology widely used in the communication field. It realizes the transmission of multiple signals on the same channel by dividing the time frame into several time slots and each signal occupies its own time slot. [0003] In a TDM system, usually the parent node receives the clock and generates the frame of the system and distributes it to each child node synchronously. The parent node may be a clock board, main control board, etc., and the child nodes may be service boards, interface boards, etc. [0004] In order to correctly multiplex signals from various channels or separate them from channels reliably, the accuracy of TDM clock and frame synchronization is particularly important. The jitter of the c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06
Inventor 方卫峰陈梁
Owner XFUSION DIGITAL TECH CO LTD
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