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Time division multiplexing system minor node frame synchronization realizing method and apparatus

A technology of a time division multiplexing system and an implementation method, which is applied in the field of the implementation method and implementation device of the frame synchronization of the sub-nodes of the time division multiplexing system, and can solve the problems of frame positioning error and poor system fault tolerance performance.

Active Publication Date: 2006-10-18
XFUSION DIGITAL TECH CO LTD
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Problems solved by technology

[0011] The present invention provides a sub-node frame synchronization implementation method and implementation device of a time division multiplexing system to solve the problems in the prior art that frame positioning errors are easily generated due to frame synchronization signal jitter and the system has poor fault tolerance performance

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  • Time division multiplexing system minor node frame synchronization realizing method and apparatus
  • Time division multiplexing system minor node frame synchronization realizing method and apparatus
  • Time division multiplexing system minor node frame synchronization realizing method and apparatus

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Embodiment Construction

[0043] See figure 2 , Is a timing diagram of the first embodiment of the method for implementing frame synchronization of the sub-nodes of the TDM system of the present invention. In the figure, the parent node of the TDM system sends a 32M (32.768MHz) clock, the frame frequency is 8KHz, and the 3-cycle low-level pulse signal is the frame. Synchronize the effective signal, and assume that a clock cycle (the second clock cycle) in the middle of the low level is the synchronization point as an example. The implementation method of sub-node frame synchronization is described as follows:

[0044] The frame synchronization arrival flag signal FSC_FLAG generates an effective signal in the second clock cycle of the low-level effective cycle of the frame synchronization signal, and changes from a low-level signal to a high-level signal (assuming the main level is valid, low level Is invalid), and its width is one clock cycle width.

[0045] The present invention adds a frame synchronizati...

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Abstract

A method for realizing subnode frame synchronization of TDM system includes adding function flag signal of frame synchronous regulation and applying it at counting of counter on subnode, detecting frame synchronous signal of father node when maximum value is achieved by subnode counter, setting said flag signal to be valid if it is high and setting flag signal to be invalid if it is low, resetting said counter and regulating local frame synchronization if said flag signal is valid or otherwise making counter count normally and holding local frame synchronization when frame synchronization arrival flag signal is valid.

Description

Technical field [0001] The invention relates to the field of communications, and in particular to a method and device for realizing frame synchronization of sub-nodes of a Time Division Multiplexing (TDM) system. Background technique [0002] TDM technology is a channel sharing technology widely used in the communication field. It realizes the transmission of multiple signals on the same channel by dividing the time frame into several time slots and each signal occupies its own time slot. [0003] In the TDM system, it is usually the parent node that receives the clock and generates the frame synchronization of the system to distribute to each child node. The parent node may be a clock board, main control board, etc., and the child node may be a service board, interface board, etc. [0004] In order to reliably multiplex each signal into or separate from the channel, the accuracy of TDM clock and frame synchronization is particularly important. The jitter of clock and frame synch...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04J3/06
Inventor 方卫峰陈梁
Owner XFUSION DIGITAL TECH CO LTD
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