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Semiconductor packages relating to thermal redistribution patterns

a technology of semiconductor packages and redistribution patterns, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of heat generation of power semiconductor chips consuming relatively high electric power, poor thermal characteristics of mcps, and different electrical power consumption of power semiconductor chips employed in each of the mcps. to achieve the effect of reducing the bottleneck phenomenon of heat transmission

Active Publication Date: 2019-09-10
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0007]According to an embodiment, a semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on a package substrate and the first and second semiconductor chips spaced apart from each other. The semiconductor package may include a thermal redistribution pattern including a first end portion disposed adjacent to the first semiconductor chip, a second end portion disposed adjacent to the second semiconductor chip, and an extension portion connected to the first end portion and the second end portion, and configured to reduce a bottleneck phenomenon of heat transmission when transferring heat from the first end portion to the second end portion.

Problems solved by technology

As each of the MCPs employs various types of semiconductor chips, the MCPs have exhibited a poor thermal characteristic.
That is, the various semiconductor chips employed in each of the MCPs may consume electric power differently.
A high power semiconductor chip consuming relatively high electric power may generate a relatively large amount of heat as compared with a low power semiconductor chip consuming relatively low electric power.
Thus, the certain region of the MCP may be excessively heated up to provide a high temperature region.

Method used

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  • Semiconductor packages relating to thermal redistribution patterns
  • Semiconductor packages relating to thermal redistribution patterns
  • Semiconductor packages relating to thermal redistribution patterns

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Embodiment Construction

[0017]The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to ordinary skill in the art to which the embodiments belong. If defined in detail, the terms may be construed according to the definitions. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

[0018]It will be understood that although the terms “first,”“second,”“third” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, but not used to define only the element itself or to mean a particular sequence.

[0019]It will also be understood that when an element or layer is referred to as being “on,”“over,”“below,”“under,” or “out...

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Abstract

A semiconductor package may include a first semiconductor chip, a second semiconductor chip, and a thermal redistribution pattern which are disposed on a package substrate. The thermal redistribution pattern may include a first end portion disposed in a high temperature region adjacent to the first semiconductor chip, a second end portion disposed in a low temperature region adjacent to the second semiconductor chip, and an extension portion connecting the first end portion to the second end portion.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2017-0152636, filed on Nov. 15, 2017, which is incorporated herein by references in its entirety.BACKGROUND1. Technical Field[0002]The present disclosure generally relates to semiconductor package technologies and, more particularly, to semiconductor packages relating to thermal redistribution patterns.2. Related Art[0003]Multi chip packages (MCPs) have been developed to integrate various types of semiconductor chips into a single package. The various types of semiconductor chips embedded in each of the MCPs may have different functions. System-in-packages (SiPs) among the MCPs have been proposed to provide high performance packages. Each of the SiPs may be configured to include a logic chip and at least one memory chip.[0004]As each of the MCPs employs various types of semiconductor chips, the MCPs have exhibited a poor thermal characteristic. That...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L23/367H01L23/373H01L25/18H01L23/00
CPCH01L23/367H01L25/18H01L24/32H01L23/3735H01L2924/1431H01L2924/1436H01L2924/15311H01L23/3736H01L23/373H01L23/31H01L23/13H01L25/074
Inventor LEE, DAE WOONG
Owner SK HYNIX INC