This invention discloses a front-end
hardware acceleration system, a program proof
hardware acceleration system, and a method. Addressing the problem that existing zero-knowledge
virtual machine front-ends still heavily rely on
software implementation, this invention proposes a dedicated heterogeneous
hardware architecture for front-end execution, main trajectory generation, and auxiliary trajectory generation. This significantly reduces front-end bottlenecks. Furthermore, the main trajectory unit, trajectory buffer unit, and auxiliary trajectory unit work collaboratively, forming a unified on-
chip processing link for program execution, main trajectory generation, and auxiliary trajectory generation. On-
chip collaborative processing of the main and auxiliary trajectories involves direct on-
chip data transfer through the trajectory buffer unit, avoiding the need to read all main trajectories back from main memory and reducing the round-trip overhead of "main trajectory in main memory—
software read back—regeneration of auxiliary trajectories." Based on the front-end
hardware acceleration system, further through units such as trajectory shaping, polynomial
processing, constraint combination, commitment generation, low-degree testing, query
initiation, and proof encapsulation, the front-end output is directly extended to the back-end
proof construction, reducing stage boundary overhead and forming an integrated end-to-end hardware
processing architecture from "program execution - trajectory generation - commitment construction - low-degree testing - query
initiation - proof encapsulation". Moreover, through the trajectory shaping unit, the front-end output can be directly connected to the back-end
proof construction, reducing additional
data format conversion overhead.