Method of testing an integrated circuit and an integrated circuit test apparatus

Abstract

A method of testing an Integrated Circuit (IC) and an IC test apparatus is provided. In one embodiment, the method of testing includes (1) applying a voltage to the IC that is not a normal operating voltage of the IC and (2) temporarily biasing a well voltage of transistors in the IC allowing screening for the normal operating voltage.

Description

TECHNICAL FIELD OF THE INVENTION [0001] The present invention is directed, in general, to Integrated Circuits (ICs) and, more specifically, to testing ICs that include a Static Random-Access Memory (SRAM) device. BACKGROUND OF THE INVENTION [0002] Memory devices are known in the art and used in, among other things, virtually all microprocessor and digital signal processor applications. Static Random Access Memory (SRAM) is one type of memory favored in many applications because it is fast and easy to use relative to many other memory types. In addition, SRAM devices that use metal-oxide-semiconductor (MOS) technology exhibit relatively low standby power and do not require a refresh cycle to maintain stored information. These attributes make SRAM devices particularly desirable for battery-powered equipment, such as laptop computers and personal digital assistants. [0003] The SRAM devices are often employed in the equipment as part of an Integrated Circuit (IC) that includes logic cir...

AI Technical Summary

Benefits of technology

The present invention provides a method and apparatus for testing ICs, specifically SRAM devices. The method involves applying a voltage to the IC that is not its normal operating voltage and temporarily biasing the well voltage of transistors in the IC to screen for the normal operating voltage. The testing can be performed at a single temperature, such as room temperature, and the method can approximate the SNM and trip voltage of the SRAM device under worst case operating conditions. The IC test apparatus includes a fixture for securing the IC, a voltage supply for providing a voltage to the IC, and a well adjuster for temporarily biasing the well voltage of transistors in the IC. The technical effects of the invention include improved low voltage screening for ICs, particularly SRAM devices, and better understanding of the worst case operating conditions of the IC.

Problems solved by technology

Testing at a low voltage extreme while at room temperature, or low voltage testing, may be used to screen-out SRAM devices that may prove unreliable or simply fail at temperatures greater than room temperature, thus, preventing evaluation of the logic circuitry.

SNM and trip voltage (so-called “Vtrip”) are parameters associated with the SRAM devices that may degrade during low voltage testing resulting in failure of the SRAM devices.

If SNM is too low, READ operations may be disrupted and if trip voltage is too low, WRITE operations may be disrupted.

Thus, the low voltage testing may result in an alpha error since a worst case condition for the SNM may not be provided during testing.

Some SRAM devices, therefore, may be deemed operationally sufficient though not truly tested at worst conditions.

Besides SNM, the low voltage testing voltage may be limited by other functions, such as the trip voltage or logic functionality.

Thus, the low voltage testing may result in a beta error since the trip voltage may degrade below a worst case condition due to a reduced voltage compared to the normal operating voltage and prevent an effective screen for other functions such as SNM.

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