Isolation structures in semiconductor integrated circuits (IC)
a technology of integrated circuits and isolation structures, which is applied in the direction of basic electric elements, electrical equipment, semiconductor devices, etc., can solve the problems of substantial addition to the fabrication cost of ic, and achieve the effect of fewer fabrication steps and simple structur
Inactive Publication Date: 2006-03-23
INT BUSINESS MASCH CORP
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Benefits of technology
The present invention provides an isolation structure and a method for forming it that is simpler and requires fewer fabrication steps than previous methods. The structure includes a semiconductor substrate and an electric isolation region embedded in the substrate, which includes a bubble-implanted semiconductor region and an electrically insulating cap region on top of the bubble-implanted semiconductor region. The method involves implanting gas bubbles into a semiconductor region of the substrate to form a bubble-implanted semiconductor region, and then creating an opening in a hard mask layer on top of the substrate and etching into the substrate via the opening to form the bubble-implanted semiconductor region. An electrically insulating cap region is then formed on top of the bubble-implanted semiconductor region. The resulting isolation structure has a simplified fabrication process and is more efficient in terms of its use of materials and resources.
Problems solved by technology
The fabrication of such typical isolation structures involve multiple fabrication steps which can substantially add to the fabrication cost of the IC.
Method used
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[0011]FIGS. 1A-1F show cross-section views of an isolation structure 100 going through different fabrication steps, in accordance with embodiments of the present invention. More specifically, with reference to FIG. 1A, in one embodiment, the fabrication process of the isolation structure 100 starts with the step of providing a semiconductor (silicon, germanium, etc.) substrate 110. Next, a pad oxide layer 120 is formed on top of the substrate 110. In one embodiment, the pad oxide layer 120 can be formed by thermally oxidizing a top surface 112 of the substrate 110.
[0012] Next, a nitride layer 130 is formed on top of the pad oxide layer 120. In one embodiment, the nitride layer 130 can be formed by CVD (Chemical Vapor Deposition) of silicon nitride on top of the pad oxide layer 120. The pad oxide layer 120 and the nitride layer 130 can be collectively referred to as the hard mask layer 120,130.
[0013] Next, with reference to FIG. 1B, in one embodiment, an opening 140 is created in t...
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A novel isolation structure in semiconductor integrated circuits (IC) and the fabrication method of the same. The isolation structure comprises (a) semiconductor a substrate, and (b) an electric isolation region embedded in and at top of the semiconductor substrate, wherein the electric isolation region comprises (i) a bubble-implanted semiconductor region and (ii) an electrically insulating cap region on top of the bubble-implanted semiconductor region.
Description
BACKGROUND OF THE INVENTION [0001] 1. Technical Field [0002] The present invention relates to semiconductor integrated circuits (IC), and more particularly, to isolation structures in semiconductor integrated circuits. [0003] 2. Related Art [0004] Typical isolation structures such as STI (Shallow Trench Isolation) structures, field oxide regions, etc., are used in a semiconductor integrated circuit (IC) to electrically isolate different devices (e.g., transistors, resistors, capacitors, etc.) formed on a same semiconductor substrate. The fabrication of such typical isolation structures involve multiple fabrication steps which can substantially add to the fabrication cost of the IC. [0005] Therefore, there is a need for a novel isolation structure (and the method of forming the same) that requires simpler and fewer fabrication steps than that of the prior art. SUMMARY OF THE INVENTION [0006] The present invention provides an isolation structure, comprising (a) a semiconductor substra...
Claims
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IPC IPC(8): H01L29/76
CPCH01L21/76224
Inventor ANDERSON, BRENT A.ELLIS-MONAGHAN, JOHN J.
Owner INT BUSINESS MASCH CORP