Non-volatile storage with reduced power consumption during read operations

a non-volatile storage and power consumption technology, applied in static storage, digital storage, instruments, etc., to achieve the effect of reducing power consumption and power consumption during read operations

Inactive Publication Date: 2008-10-30
SANDISK TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012]The present invention addresses the above and other issues by providing non-volatile storage in which power consumption during a read operation is reduced. Power consumption is reduced in particular when many of the storage elements are in an erased, e.g., unprogrammed, state.

Problems solved by technology

However, one issue with memory devices is the need to reduce power consumption whenever possible, e.g., to reduce battery consumption and heat build up in portable electronic devices which use non-volatile memory.

Method used

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  • Non-volatile storage with reduced power consumption during read operations
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  • Non-volatile storage with reduced power consumption during read operations

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Embodiment Construction

[0039]The present invention provides a non-volatile storage in which power consumption during a read operation is reduced.

[0040]One example of a memory system suitable for implementing the present invention uses the NAND flash memory structure, which includes arranging multiple transistors in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors, 100, 102, 104 and 106, in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 gates the NAND string connection to bit line 126. Select gate 122 gates the NAND string connection to source line 128. Select gate 120 is controlled by applying the appropriate voltages to control gate 120CG. Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG. Each of ...

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Abstract

A non-volatile storage device in which power consumption is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is related to co-pending, commonly assigned U.S. patent application Ser. No. ______, filed herewith, titled “Reducing Power Consumption During Read Operations In Non-Volatile Storage” (docket no. SAND-1228US0), incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to non-volatile memory.[0004]2. Description of the Related Art[0005]Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portio...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C8/08
CPCG11C16/3418
Inventor SEKAR, DEEPAK CHANDRAMOKHLESI, NIMASO, HOCK C.
Owner SANDISK TECH LLC
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