Counter of semiconductor device
a counter and semiconductor technology, applied in the field of counters used in semiconductor devices, can solve the problems of increasing propagation delay, unstable value, and half adder structure carrying propagation delay, and achieve the effect of reducing the propagation time delay of the counter and minimizing data skew
Inactive Publication Date: 2009-11-19
SK HYNIX INC
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- Application Information
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Benefits of technology
The present invention relates to a counter that can reduce delay and minimize data skew. The invention includes a D-flipflop and two MUXs that select and transfer data signals. The counter can be used in a 2-bit or n-bit counter. The technical effect of the invention is to improve the speed and accuracy of data processing.
Problems solved by technology
In the case of the ripple counter, the counter can be designed with a minimum area, but has increased propagation delay due to delays accumulated at every stage and may have an unstable value due to increased data skew.
However, the counter employing the half adder structure has a carry propagation delay as a carry value can ripple across the half adder structure.
Accordingly, the CLA structure has disadvantage in rising / falling times of the output terminal.
Method used
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[0018]Specific embodiments according to the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the disclosed embodiments, but may be implemented in various ways. The embodiments are provided to complete the disclosure of the present invention and to allow those having ordinary skill in the art to understand the scope of the present invention. The present invention is defined by the category of the claims.
[0019]FIG. 1 is a circuit diagram showing a unit counter block of a counter circuit in accordance with an embodiment of the present invention. A unit counter block includes a D-flipflop 110, a selector (or multiplexor (MUX)) 120, and an output unit 130. The D-flipflop 110 holds an input signal D during one clock cycle according to a clock signal CLK and outputs a delayed signal. The MUX 120 selects and transfers a first output signal Q or a second output signal / Q of the D-flipflop to the input signal D o...
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The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal.
Description
CROSS-REFERENCES TO RELATED APPLICATION[0001]The present application claims priority to Korean patent application number 10-2008-0044124, filed on May 13, 2008, which is incorporated by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a counter used in semiconductor devices, and more specifically to a counter which can reduce propagation delay.[0003]Counters used in semiconductor devices can be largely divided into two types. These are a counter employing a half adder structure and a ripple counter employing simple toggling. In the case of the ripple counter, the counter can be designed with a minimum area, but has increased propagation delay due to delays accumulated at every stage and may have an unstable value due to increased data skew.[0004]Meanwhile, the counter employing the half adder structure has an increased area compared with the ripple counter, but has better characteristics in terms of data skew, since data output is synchroni...
Claims
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IPC IPC(8): H03K23/00
CPCH03K23/50H03K23/40H03K23/00
Inventor LIM, SANG OHJEONG, BYOUNG KWANYOON, MI SUN
Owner SK HYNIX INC