Static Power Reduction in Caches Using Deterministic Naps

Abstract

The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Description

CLAIM OF PRIORITY[0001]This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 61 / 983,216 filed 23 Apr. 2014.TECHNICAL FIELD OF THE INVENTION[0002]The technical field of this invention is cache memory for data processors.BACKGROUND OF THE INVENTION[0003]Phased caches were previously introduced as cache architecture to reduce the redundant and high-energy consumption caused by reading all data ways on every cache access even though only one of them will be used if the access hits the cache. Phased caches do not query the data arrays in the first cycle of access but rather, wait until a hit is determined before accessing the specific data way hit. This saves dynamic read energy but static energy consumption is not reduced since both the tag and data arrays are ON throughout the program execution.[0004]The rapid increase in microprocessor speed has exceeded the rate of improvement in DRAM (Dynamic Random Access Memory) speed in recent years. This ...

AI Technical Summary

Benefits of technology

[0008]This invention deterministically powers ON only data RAM lines or group of lines that will be accessed in the immediate future while keeping all other lines powered down. The tag RAMs remain ON to avoid any extra latency associated with powering on a tag RAM/line that is to be accessed. The data RAM on the other hand is deterministically powered ON before access with no extra latency. This is possible in phased caches because hit determination takes a minimum of 2-cycles before data RAM access. Therefore, the power-ON sequence for a set/set-group is triggered on every access to the

Problems solved by technology

This widening performance gap between processors and memories has created several challenges for computer designers since memory performance can easily become a bottleneck to overall system performance.

Therefore, using a larger cache could increase the access hit rate, which in turn improves processor speed but this comes at a cost—increased hardware and higher static and dynamic energy consumption.

As a result, there is usually a trade-off between energy and performance in memory system design, since not all accessed memory locations can be stored in faster memories such as caches.

Current memory systems designed with SRAMs, DRAMs and/or CAMs, have not been able to catch up with processor performance.

While these large caches offer improved performance, they also increase the power consumed by the processor.

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