Methods of forming different sized patterns

Abstract

A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends from the fourth opening and penetrates the underlying layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2015-0048672, filed on Apr. 6, 2015, which is herein incorporated by reference in its entirety as set forth in full.BACKGROUND[0002]1. Technical Field[0003]Various embodiments of the present disclosure relate to semiconductor technologies and, more particularly, to methods of forming patterns having different critical dimensions (CDs).[0004]2. Related Art[0005]To increase integration density of semiconductor devices comprised of integrated circuits, it may be necessary to reduce an area occupied by a unit cell of the semiconductor devices and to increase the number of discrete devices such as transistors, resistors, capacitors or the like, integrated in a limited area of a semiconductor substrate. Various techniques have been attempted to realize fine pattern structures having a nano-scale critical dimension (CD), that is, a size ranging from a few n...

AI Technical Summary

Benefits of technology

The patent text describes methods for forming patterns using a block copolymer layer. The methods involve forming a template portion to provide a first opening trench portion surrounding a first isolated pattern and an array of pillars on an underlying layer. A separation wall layer is then formed to cover the pillars and the template portion. A block copolymer layer is then formed to fill the gaps between the pillars and the template portion. Openings are then formed by selectively removing certain portions of the separation wall layer and the block copolymer layer. The methods allow for the formation of patterns with different sizes and shapes.

Problems solved by technology

It is difficult to form nano-scale fine patterns of the semiconductor devices only with a photolithography process.

Image resolution limits of lithography apparatuses for the photolithography process may be caused by the nature of optical systems for the photolithography process and wavelengths of lights generated from light sources of the optical systems.

However, it is difficult to merely apply a direct self-assembly (DSA) of polymer molecules to methods of forming a plurality of patterns having different pitches for example, different widths or different spaces.

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