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Memory Device and Erasing and Verification Method Thereof

a technology of memory devices and verification methods, applied in the field of memory devices and erasing and verification methods thereof, can solve problems such as false error verification stages, and achieve the effect of increasing channel discharging time and avoiding false error verification

Active Publication Date: 2021-10-28
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0007]It is therefore an objective of the present invention to provide a memory device and erasing and verification method thereof capable of increasing channel discharging time to avoid false error verification.

Problems solved by technology

However, in the 3D NAND Flash, a false error may occur in the verification stage.

Method used

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  • Memory Device and Erasing and Verification Method Thereof
  • Memory Device and Erasing and Verification Method Thereof
  • Memory Device and Erasing and Verification Method Thereof

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Embodiment Construction

[0019]In the following detailed description, reference is made to the accompanying drawings that show, byway of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined onl...

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Abstract

A memory device includes a plurality of memory blocks, and a control circuit. A selected memory block of the plurality of memory blocks comprises a top select gate, a bottom select gate, a plurality of word lines, a common-source line, and a P-well. The control circuit performs an erasing and verification method, wherein the erasing and verification method includes erasing the selected memory block during an erasing stage; and maintaining the bottom select gate to be turned on during a maintaining period before the top select gate are turned on during a verification stage.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of PCT Application No. PCT / CN2020 / 087356 filed on 2020 Apr. 28, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION1. Field of the Invention[0002]The present invention relates to a memory device and erasing and verification method thereof, and more particularly, to a memory device and erasing and verification method thereof capable of increasing channel discharging time to avoid false error verification.2. Description of the Prior Art[0003]Semiconductor memories are widely used in various electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices and non-mobile computing devices. A nonvolatile memory allows information to be stored and retained. Examples of the nonvolatile memory comprises a flash memory (e.g., NAND type and NOR type flash memory) and electrically erasable program...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C16/14G11C16/34
CPCG11C16/14G11C16/0483G11C16/3445G11C16/16G11C16/3472G11C11/5635G11C2211/5621
Inventor LI, KAIWEIJIA, JIANQUANLIU, HONGTAOZHANG, AN
Owner YANGTZE MEMORY TECH CO LTD