Aggregation of storage elements into stations and placement of same into an integrated circuit or design

Abstract

The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.

Description

1. Field of the InventionThe invention relates generally to semiconductor integrated circuits as well as designs and design tools therefor and, more specifically, to techniques for placement of storage stations in into an integrated circuit or design.2. Description of the Related ArtTiming-critical paths (or nets) of a semiconductor integrated circuit can affect delivery of signals in a way that limits achievable operating frequency. Indeed, one of the significant limiting factors in the design of modern, high-performance microprocessors is interconnect delay. Typically, interconnect delay, rather than logic delay limits operating frequency of circuits designed to operate in the gigahertz range.A common design technique employed to overcome the limitations imposed by certain timing critical paths, including those that arise due to maxtime constraint violating interconnect delays, is to insert storage elements (e.g., flip-flops or flops), into the timing-critical paths. In effect, th...

AI Technical Summary

Benefits of technology

This approach reduces the number of storage elements required, enabling compact layouts and minimizing placement conflicts, thereby improving the performance of high-speed semiconductor designs by allowing operation at frequencies unachievable with conventional techniques.

Problems solved by technology

Indeed, one of the significant limiting factors in the design of modern, high-performance microprocessors is interconnect delay.

Typically, interconnect delay, rather than logic delay limits operating frequency of circuits designed to operate in the gigahertz range.

Unfortunately, in complex integrated circuit designs, the number of timing-critical paths (or nets) can be quite large, numbering in the thousands or more, and placement rapidly becomes intractable, particularly when layout constraints are considered.

In either case, practical and computational requirements (including those associated with extended design and testing cycles) generally conflict with the goal of placing large numbers of flops into a design.

In some variation, a substantial number of the timing-critical circuit paths spanned by a particular storage station exhibit generally uncorrelated timing requirements.

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