The invention provides a buck converter and an operation method thereof. The buck converter includes a power stage, a feedback network, a control loop, a logic circuit, a driver circuit, and a bypass detector. The power stage comprises an input end and an output end. The feedback network is coupled to the power stage for generating a feedback voltage according to the output voltage. The control loop comprises an error amplifier and a comparator. The error amplifier is used for generating an error voltage by comparing a reference voltage with a feedback voltage, and the comparator is coupled to the error amplifier and is used for generating a comparatorsignal according to the error voltage. The logic circuit is used for generating a logic controlsignal according to a group of control signals to realize a control scheme. The driving circuit is used for driving the power stage according to the logic controlsignal. The bypass detector is used for comparing the input voltage with a preset threshold value and correspondingly generating a bypass mode signal.
A controller for a voltage converter, such as a buck converter, includes: a switching regulator circuit having high side and low side switches; comparators configured to compare a voltage of an output circuit to reference voltages; and a control circuit coupled to the current comparators, configured to receive outputs from the comparators, and configured to generate a control signal for alternatingly switching the high side and low side switches off and on, such that the low side switch is off when the high side switch is on, and the high side switch is off when the low side switch is on, and wherein the control circuit includes a latching circuit configured to latch a signal corresponding to at least one of the outputs from the comparators. A method of operating a buck converter in connection with a fixed high-frequency automotive radarsystem, with reliable over-current detection, is also disclosed.
A voltage down converter includes a fast response circuit, a compensator coupled to an output, an interleaving logic circuit coupled to the compensator, a plurality of pulse width modulationsignal generators, a plurality of OR gates coupled to corresponding pulse width modulationsignal generators, a plurality of power stages coupled to corresponding OR gates, a plurality of inductors and an output capacitor. Each pulse width modulationsignal generator is coupled to the interleaving logic circuit, the output and an input. The fast response circuit includes a voltage droop sensor coupled to the output, a load frequency sensor coupled to the output, a fast response signal generator coupled to the voltage droop sensor, a maximum fast response signal generator coupled to the voltage droop sensor and the load frequency sensor, and an AND gate coupled to the fast response signal generator, the maximum fast response signal generator and the plurality of OR gates.