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Method for forming power devices and structure thereof

A power device and power technology, applied in the field of forming semiconductor devices, can solve problems such as difficulty in keeping the power tube off, difficulty in turning on and off the transistor, power loss, etc.

Inactive Publication Date: 2007-09-26
SEMICON COMPONENTS IND LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Another issue is heat dissipation and power loss
Difficulty turning the transistor on and off results in slow rise and fall times which will increase the power dissipation of the transistor
[0005] Also, it's hard to keep the power tubes off

Method used

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  • Method for forming power devices and structure thereof
  • Method for forming power devices and structure thereof
  • Method for forming power devices and structure thereof

Examples

Experimental program
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Embodiment Construction

[0014] The present description includes a method of forming a power device having, among other features, reduced turn-on and turn-off times, increased immunity to transient off-states, and predictable timing.

[0015] FIG. 1 schematically illustrates portions of an embodiment power device 10 . Device 10 includes a power MOSFET 11 formed in a semiconductor die. Device 10 also includes a driver circuit 12 formed on a separate semiconductor die and connected to drive power MOSFET 11 . In the preferred embodiment, the power MOSFET 11 and driver circuit 12 are attached to a lead frame and packaged in the same semiconductor package. In another embodiment, the driver circuit 12 and the power MOSFET 11 may be formed in different package configurations including separate packages.

[0016] The power MOSFET 11 includes a power transistor 27 and a pull-down transistor 28 . Power MOSFET 11 is typically a large semiconductor device and is generally formed from a number of transistors co...

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PUM

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Abstract

A method of forming a power device (10) includes forming a power transistor (27) and a pull-down transistor (28) on a semiconductor die (36). The pull-down transistor (28) is enabled to rapidly and predictably disable the power transistor (27). The pull-down transistor (28) remains enabled for a first time period during the enabling of the power transistor (27) to facilitate rapidly and predictably enabling the power transistor (27).

Description

technical field [0001] The present invention relates generally to electronics, and more particularly to methods and structures for forming semiconductor devices. Background technique [0002] In the past, the semiconductor industry used a variety of techniques to control metal-oxide-semiconductor (MOS) power transistors. Typical MOS power transistors are large and dissipate large amounts of power, so MOS power transistors are generally formed on a single semiconductor die. Typically, such a power transistor is driven by a semiconductor device external to the power transistor. The drive transistor is typically a small MOS transistor connected in a totem pole structure to provide active pull-up and pull-down of the power transistor gate. [0003] One problem with this method and device is inaccurate timing prediction. MOS power transistors typically have large gate capacitance and large inductance due to bond wires connecting the gate to external pins. Because of this capa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H03K17/0412
CPCH03K17/04123
Inventor 本杰明·M.·赖斯
Owner SEMICON COMPONENTS IND LLC