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Convolutional interleaver, convolutional deinterleaver, convolutional interleaving method, and convolutional deinterleaving method

一种解交错、卷积的技术，应用在使用卷积码纠错/检错、使用交错技术纠错/检错、数据表示错误检测/纠正等方向，能够解决电路规模变大等问题

Inactive Publication Date: 2008-03-12
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] Such a convolution interleave device in FIG. 13 and a convolution deinterleave device in FIG. 14 require a plurality of multi-segment shift registers. As other existing examples to solve this problem, there is a convolution interleave device composed of RAM, so there is a circuit scale big problem

Method used

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  • Convolutional interleaver, convolutional deinterleaver, convolutional interleaving method, and convolutional deinterleaving method
  • Convolutional interleaver, convolutional deinterleaver, convolutional interleaving method, and convolutional deinterleaving method
  • Convolutional interleaver, convolutional deinterleaver, convolutional interleaving method, and convolutional deinterleaving method

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Embodiment 1

[0111] The convolutional interleave device of the first embodiment can suppress increases in the circuit scale and power consumption of RAM peripheral circuits by concentrating the address counters of the RAM in units of two channels.

[0112] The configuration of the convolutional interleave apparatus according to the first embodiment will be described with reference to FIG. 1. FIG.

[0113] In the convolutional interleaving device of the present embodiment 1, 53 is a single-port RAM (the first storage device in the third aspect) that reads out data to the readout device 54, and 46 is an output of the input data 61 of the convolutional interleaving device. Input data control device for register 49, output signal selector 55 and shift register 59, 50 is to output control signal to input data control device 46, upper address generation device 41, lower address selector 44, shift register selector 59 and 60 and the selection signal generating device of the RAM control device 61,...

Embodiment 2

[0146] The convolution deinterleaving apparatus according to the second embodiment can suppress the increase in the circuit scale and power consumption of the peripheral circuit of the RAM by concentrating the address counters of the RAM with 2 channels as a unit.

[0147] The configuration of the convolutional deinterleaving apparatus according to the second embodiment will be described with reference to FIG. 4 .

[0148]In the convolution deinterleaving device of the present embodiment 2, 83 is a single-port RAM (the first storage device of the eleventh aspect) that outputs data to the readout device 84, and 76 is the input data of the convolution deinterleaving device 91 is output to the input data control device of bit coupling device 77, register 791 and shift register selector 89, and 80 is to output the control signal to upper address generation device 71, lower address selector 74, input data control device 76, shift Register selectors 89, 90 and a selection signal gen...

Embodiment 3

[0184] In the convolutional interleave device of the third embodiment, the address counters of the RAM are concentrated in units of 2 channels, thereby suppressing increases in the circuit scale and power consumption of the peripheral circuits of the RAM. In addition, by realizing the delay to be performed only with the RAM, it is possible to configure a device in which memory circuits of different types are not mixed.

[0185] The configuration of the convolutional interleave device according to the third embodiment will be described with reference to FIG. 7. FIG.

[0186] In the convolutional interleaving device of Embodiment 3, 213 is a single-port RAM (storage device in the sixth aspect) that outputs data to the readout device 214, and 206 is outputting the input data 221 of the convolutional interleaving device to the bit-connected The input data control device of device 207 and output signal selector 215, 208 is the register that outputs data to bit coupling device 207, ...

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Abstract

To provide a convolutional interleave device for improving integration degree and reducing power consumption. This device is provided with a RAM area..., 123-(N / 2-1),..., 123-((C-1) / 2-1) for delaying data and shift registers 122-0,..., 122-((C-1) / 2), and for the RAM area, an address counter is made common in two channels. Input data are selected by a selector 120, the data are successively inputted to the RAM area..., 123-(N / 2-1),..., 123-((C-1) / 2-1) and the shift registers 122-0,..., 122-((C-1) / 2) and the data are taken out in synchronism with that by the selector 121.

Description

[0001] This application is a divisional application with the application number 99107658.3, the title of the invention is "Convolutional interleaving device, convolutional deinterleaving device, convolutional interleaving method and convolutional deinterleaving method", and the filing date is April 27, 1999. technical field [0002] The present invention relates to a convolution interleave device, a convolution deinterleave device, a convolution interleave method and a convolution Deinterleaving method. technical background [0003] The convolutional interleave method is effective as a measure against burst errors. [0004] When satellite broadcasting is described as an example, radio waves from a TV station on the ground are transmitted to a satellite, relayed by the satellite, and received by a satellite broadcast receiver installed at home. [0005] Among these, radio waves transmitted from television stations to households via satellites are disturbed when there is thun...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/23H03M13/27
CPCH03M13/2764H03M13/6505H03M13/2732H03M13/6502H03M13/27
Inventor 古谷专一中仓康浩
Owner PANASONIC CORP