Convolution cross and deconvolution cross device and method thereof
A de-interleaving and convolution technology, applied in the direction of error correction/error detection using convolutional codes, error correction/error detection using interleaving technology, and data representation error detection/correction, etc.
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Embodiment 1
[0111] The convolutional interleave device of the first embodiment can suppress increases in the circuit scale and power consumption of RAM peripheral circuits by concentrating the address counters of the RAM in units of two channels.
[0112] The configuration of the convolutional interleave apparatus according to the first embodiment will be described with reference to FIG. 1. FIG.
[0113] In the convolutional interleave device of the present embodiment 1, 53 is a single-port RAM (the first storage device in the third aspect) that outputs data to the readout device 54, and 46 is the output data 61 of the convolutional interleave device to The register 49, the output signal selector 55 and the input data control device of the shift register 59, the 50 is to output the control signal to the input data control device 46, the upper address generation device 41, the lower address selector 44, and the shift register selector 59 And 60 and the selection signal generator of the RAM...
Embodiment 2
[0146] The convolution deinterleaving apparatus according to the second embodiment can suppress the increase in the circuit scale and power consumption of the peripheral circuit of the RAM by concentrating the address counters of the RAM with 2 channels as a unit.
[0147] The configuration of the convolutional deinterleaving apparatus according to the second embodiment will be described with reference to FIG. 4 .
[0148]In the convolution deinterleaving device of the present embodiment 2, 83 is a single-port RAM (the first storage device of the eleventh aspect) that outputs data to the readout device 84, and 76 is the input data of the convolution deinterleaving device 91 is output to the input data control device of bit coupling device 77, register 791 and shift register selector 89, and 80 is to output the control signal to upper address generation device 71, lower address selector 74, input data control device 76, shift Register selectors 89, 90 and a selection signal gen...
Embodiment 3
[0184] In the convolutional interleave device of the third embodiment, the address counters of the RAM are concentrated in units of 2 channels, thereby suppressing increases in the circuit scale and power consumption of the peripheral circuits of the RAM. In addition, by realizing the delay to be performed only with the RAM, it is possible to configure a device in which memory circuits of different types are not mixed.
[0185] The configuration of the convolutional interleave device according to the third embodiment will be described with reference to FIG. 7. FIG.
[0186] In the convolutional interleaving device of Embodiment 3, 213 is the single-port RAM (storage device of the sixth aspect) that outputs data to the readout device 214, and 206 is outputting the input data 221 of the convolutional interleaving device to the bit-connected The input data control device of device 207 and output signal selector 215, 208 is the register that data is output to bit coupling device 2...
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