System and method for restricting increasing register addressing space in instruction width processor

Abstract

A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommodate shortened instruction words in multiple-issue processors. These components are arranged to permit greater access to registers by instructions, thereby permitting reduction of the word length, as compared to conventional very long instruction word (VLIW) processors.

Description

technical field [0001] The present invention relates to a computer architecture, in particular to a computer processor. Background technique [0002] Very long instruction word or VLIW (very long instruction word; VLIW) processor is a known technology, and figure 1 is to show an example of it. Such as figure 1 As shown in , a conventional processor includes: an instruction decoder 105, a control sequence hardware 115, an input / output buffer 130, one or more register arrays 110, and one or more functional units 120 (which also Known as the issue slot). [0003] In this architecture, instructions enter the instruction decoder 105 from an external source. The command decoder 105 converts the received command into a wider but easier to handle decoded internal format. The decoded instruction is then used to control the operation of the data path components (including the I / O buffer 130, the register set 110 and the functional unit 120). Since the operations of conventional ...

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This is often the main limiting factor in system performance

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